16 | Keysight | M9195A PXIe Digital Stimulus/Response with PMU: 250 MHz, 16-channel - Data Sheet
Technical specifications and characteristics
Timing and Trigger Specifications and Characteristics
Channel clock
Number of independent clock domains
1 - when configured as a single, 16 channel site
4 - when configured as 4, 4 channel sites
Number of independent clocks depends on the
number of sites selected
Maximum RZ clock rate on a data channel
Minimum RZ clock rate on a data channel
Clock jitter
250 MHz
5 mHz
<25 ps RMS
Internal reference clock
Frequency
100 MHz
Accuracy
±25 ppm
Period jitter
<2 ps RMS
Reference clock sources
External reference clock input (SMB front panel)
Input frequency
PXI_CLK100, PXIe-DSTARA, CLK IN
10 MHz or 100 MHz
50 Ω
Input impedance (CLK IN)
Input voltage range (CLK IN)
Lock range accuracy
Nominal, AC coupled
+1.8 V to + 3.3 V
±25 ppm
Duty cycle
40 to 60%
Channel timing (per channel)
Waveform timing change
Edge placement resolution (EPR)
Stimulus delay resolution per test:
Per vector
1 ns minimum
Dependent on waveform table period
Edge Placement Resolution (EPR) is
specified at the time of test activation.
– For EPR £ 1 ns and ≤ 1.3 ns
– For EPR > 1.3 ns
24 ps
EPR
Stimulus delay range per test
254 x EPR
Response delay compensation resolution per test:
Edge Placement Resolution (EPR) is
specified at the time of test activation.
– For EPR £ 1 ns and ≤ 1.3 ns
– For EPR > 1.3 ns
24 ps
EPR
Response delay compensation range per test
Channel-to-channel skew
254 x EPR
±300 ps
At 1ns EPR
Trigger characteristics
Trigger sources
Software (API-driven)
Waveform characteristics
Number of waveform tables
Number of waveform characters
Generation waveform iteration count
Receive post trigger sampling
32
15 (user definable)
Once, n times, infinite
0 to full record waveform
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