04 | Keysight | M9195A PXIe Digital Stimulus/Response with PMU: 250 MHz, 16-channel - Data Sheet
Flexible digital pattern generation
With the included software tools, easily create, modify and reuse previously defined pat-
terns. Pattern timing is controlled using up to 32 waveform tables. Within the waveform
table, each of the 15 user-defined vector characters is translated into one of the follow-
ing hardware actions: Force High/Low (U/D), Force to previous state (P), Stop Forcing
(Z), Compare High/Low (H/L), Compare to Tri-state (T), Don’t Compare (X). Each vector
period has two drive edges that are used when forcing a digital state and one receive
edge used to compare digital data from the DUT. Edge placement resolution can be set
as low as 1 ns and edge placement can vary from period to period so that oversampling
is not required. The two drive edges enable the user to easily create a clock or other RZ
formats from a single vector without requiring two vectors. The flexibility of the drive
edges allow them to be changed on a per vector basis using the vector characters or by
referencing a different waveform table.
The combination of the waveform tables and edge placement resolution simplifies the
pattern programming. Variables and equations can be defined to allow the user to simul-
taneously modify timing relationships and edge placement.
Once compiled, the digital patterns are stored in the PXI DSR’s on-board pattern cache.
The PXI DSR executes the patterns from the cache in order to provide high test through-
put. High-level pattern sequencing commands allow for high level macros which can be
used to define timing sets, counted and uncounted looping of pattern blocks, conditional
execution based upon matching parallel or serial patterns, or wait for software trigger
advance.
Advance timing capabilities
Change pattern values that have been downloaded to the cache without recompiling.
Pattern values can replace either parallel vectors or serial patterns. These powerful
features allow you to quickly modify patterns directly from the API. The user can create
pattern templates that are used to read or write to the DUT, then provide the vector
information directly from the API.
Variables can be modified at the API level without recompiling the test pattern. This
allows the user to control pattern timing or levels directly from the API. These advanced
capabilities useful for test applications such as a timing or voltage level shmoo.
Serial and parallel digital bus emulation
The combination of the flexible pattern timing and sequencing features, enables the PXI
DSR to emulate a wide variety of standard or custom serial/parallel protocols such as
SPI and RFFE.
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