18 | Keysight | M8195A 65 GSa/s Arbitrary Waveform Generator and M8197A Multi-Channel Synchronization Module - Data Sheet
Variable channel delay
In order to compensate for external cable length differences as well as the initial skew, channels 1, 2, 3 and 4 can be individually
delayed with a very high timing resolution. There are two possibilities to adjust the variable channel delay:
– The sample clock delay can be changed in discrete steps. The step size is 1 / DAC Sample Frequency. E.g. the step size is 15.625
ps for a DAC Sample Frequency of 64 GHz.
– The FIR delay can be used for sub sample delay adjust. Note: This delay functionality uses a digitally implemented FIR filter with
limited length and accuracy. As a result the output signal may show some degradation when using the FIR delay adjust.
M8195A
Sample clock delay range
FIR delay range
0 … 95 sample clocks
Sample Rate Divider = 1
Sample Rate Divider = 2
Sample Rate Divider = 4
FIR delay resolution
-50 ps…+50 ps
-100 ps…+100 ps
-200 ps…+200 ps
10 fs
Variable module delay
In order to compensate for external cable length differences as well as the initial skew, channels 1, 2, 3 and 4 can be jointly delayed
with a very high timing resolution. In case the M8197A synchronization module is used to configure a synchronous system, the variable
delay can be used to align the channels of multiple M8195A modules.
Modifying the variable delay always affects the delay of all four channels.
E.g. setting the variable delay to 10 ps has the following effect. Out 1, 2, 3 and 4 are delayed by 10 ps with respect to trigger/gate input
and event input.
M8195A
Delay range
0 ns to 10 ns
50 fs
Delay resolution
Delay accuracy
± 10 ps (typ)
FIR filter
Each channel in the M8195A has an FIR filter with programmable coefficients in front of its respective DAC. The FIR filters are used to
realize variable channel delay and waveform interpolation with sample rate divider 2 and 4. The following presets are available for the
FIR filter coefficients: Nyquist, Low Pass, Linear Interpolation, Zero Order Hold and User Defined. The number of taps of each filter is
16 when internal memory is used and depends on the sample rate divider when extended memory is used as shown in the following
table:
Sample Rate Divider
Taps
16
Memory Sample Rate
DAC Sample Rate
1
2
3
53.76 GSa/s … 65.00 GSa/s
26.88 GSa/s … 32.50 GSa/s
13.44 GSa/s … 16.25 GSa/s
53.76 GSa/s … 65.00 GSa/s
53.76 GSa/s … 65.00 GSa/s
53.76 GSa/s … 65.00 GSa/s
32
64
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