07 | Keysight | M3100A PXIe Digitizer with Optional Real-Time Sequencing and FPGA Programming - Data Sheet
Data acquisition blocks (DAQs) specifications
M3100A-CH4
Typ
M3100A-CH8
Typ
Parameter
Min
Max
Min
Max Units
Comments
General specifications
DAQs
4
5
8
5
1 per channel
Aggregated speed
Acquisition burst multiple
Acquisition RAM capacity
Acquisition RAM capacity effic.
Trigger
400
800 MSa/s
For all onboard DAQs combined
Samples Burst length must be a multiple of this value
957M Samples Maximum depends on onboard RAM
15
957M
15
93.5
93.5
%
Effic. = waveform size / waveform size in RAM
Selec.
Selec.
Hardware trigger (analog channels, input
trigger, backplane triggers), software trigger
DAQ specifications
Speed
100
100 MSa/s
Bits
Per DAQ
Resolution
14
14
Table 3. Data acquisition blocks (DAQs) specifications
Clock system specifications
M3100A-CH4
M3100A-CH8
Min Typ Max Units
Parameter
Min
Typ
Max
Comments
General specifications
Clock frequency
100
100
MHz
Table 4. Clock system specifications
System specifications
Environmental specifications (PXI Express)
M3100A-CH4
M3100A-CH8
Typ
Parameter
Min
Typ
Max
Min
Max Units
Comments
System bus
Slots
1
1
Slot
PXI Express (CompactPCI Express compatible)
Automatic gen negotiation, chassis dependent
Automatic lane negotiation, chassis dependent
PCI Express type
PCI Express link
PCI Express speed
Sustainable throughput
Power dissipation
3.3V PXIe power supply
12V PXIe power supply
Gen 1
1
Gen 2 Gen 1
Gen 2
4
–
4
1
Lanes
400
200
1600
800
400
200
1600 MBytes/s Depends on # of lanes, chassis, congestion, and more
800 MPoints/s Depends on # of lanes, chassis, congestion, and more
1.5
2
1.5
2
A
A
~ 5 W
~ 24 W
Table 5. Environmental specifications (PXI Express)
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