06 | Keysight | M3100A PXIe Digitizer with Optional Real-Time Sequencing and FPGA Programming - Data Sheet
I/O specifications
Analog input characteristics
Number of channels
CH4 or CH8
Sampling rate
100 MSa/s option CLF
Configurable inputs: impedance
Configurable inputs: Coupling
Input voltage range (50Ω)
Input voltage range (HiZ)
Bandwidth limit filters
50Ω or 1 MΩ (HiZ)
AC or DC
400 mVpp to 6Vpp (continue: variable attenuator at input)
200 mVpp to 20Vpp (continue: variable attenuator at input)
100 MHz
Effective number of bits (ENOB)1
10.8 bits @30MHz (typical)
−142 dBm/Hz @30 MHz (typical)
67 dB @30 MHz (typical)
79 dBc (typical)
Noise floor
SINAD
Spurious free dynamic range (SFDR) + Total Harmonic Distorsion
1. measured at -1 DBFS input signal with 1.5 Vpp 50Ω
Table 2a.
M3100A
Parameter
Min
Typ
Max
Units
Comments
Reference clock output
Frequency
10 or 100
MHz
mVpp
dBm
Ω
Generated from the internal clock. User selectable
Voltage
800
2
On a 50 Ω load
On a 50 Ω load
AC coupled
Power
Source impedance
50
External I/O trigger/marker
VIH
2
0
5
V
VIL
0.8
3.3
0.5
V
VOH
2.4
0
V
On a high Z load
On a high Z load
VOL
V
Input impedance
Source impedance
Speed
10
K Ω
–
TTL
500
Mbps
Table 2b.
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