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86115D-104 参数 Datasheet PDF下载

86115D-104图片预览
型号: 86115D-104
PDF下载: 下载PDF文件 查看货源
内容描述: [Wide-Bandwidth Oscilloscope Mainframe and Modules]
分类和应用:
文件页数/大小: 37 页 / 3203 K
品牌: KEYSIGHT [ Keysight Technologies ]
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06 | Keysight | Infiniium DCA-X 86100D Wide-Bandwidth Oscilloscope Mainframe and Modules - Data Sheet  
Specifications (Continued)  
Mainframe specifications (Continued)  
Option STR (standard trigger)  
Option ETR (enhanced trigger)  
Trigger modes  
Internal trigger 1  
External direct trigger 2  
Limited bandwidth 3  
Full bandwidth  
Free run  
Free run  
DC to 100 MHz  
DC to 3.2 GHz  
DC to 100 MHz  
DC to 3.2 GHz  
External divided trigger  
PatternLock  
Module bay trigger 7  
Jitter  
N/A  
N/A  
N/A  
3 to 13 GHz (15 GHz, 32 GHz with Option PTB)  
50 MHz to 13 GHz (50 MHz to 15 GHz)  
Yes, supported  
Characteristic  
< 1.0 ps RMS + 5*10E-5 of delay setting 4  
1.5 ps RMS + 5*10E-5 of delay setting 4  
N/A  
1.2 ps (750 fs Option PTB) RMS for time delays less than 100 ns 6  
1.7 ps (1.2 ps Option PTB) RMS for time delays less than 100 ns 6  
1.2 ps (750 fs) (50 MHz to 32 GHz) in PTB mode 8: 200 fs  
(2.4 to 4 GHz) 120 fs (4 to 9 GHz) 90 fs (9 to 44 GHz)  
Maximum  
Option PTB  
Trigger sensitivity  
200 mVpp (sinusoidal input or 200 ps  
minimum pulse width)  
200 mVpp sinusoidal input: 50 MHz to 13 GHz, (to 32 GHz with  
Option PTB)  
Trigger configuration  
Trigger level adjustment  
Edge select  
–1 to + 1 V  
Positive or negative  
Normal or High sensitivity  
AC coupled  
N/A  
N/A  
Hysteresis 5  
Trigger gating  
Gating input levels  
(TTL compatible)  
Gating delay  
Disable: 0 to 0.6 V, Enable: 3.5 to 5 V  
Pulse width > 500 ns, period > 1 μs  
Disable: 27 μs + trigger period +  
Maximum time displayed  
Enable: 100 ns  
Trigger impedance  
Nominal impedance  
Reflection  
50 Ω  
< 10% for 100 ps rise time  
3.5 mm (male)  
Connector type  
Maximum trigger signal  
2 V peak-to-peak  
1. The freerun trigger mode internally generates an asynchronous trigger that allows viewing the sampled signal amplitude without an external trigger signal  
but provides no timing information unless a precision timebase is used in Eye/Mask mode. Freerun is useful in troubleshooting external trigger problems.  
2. The sampled input signal timing is recreated by using an externally supplied trigger signal that is synchronous with the sampled signal input.  
3. The DC to 100 MHz mode is used to minimize the effect of high frequency signals or noise on a low frequency trigger signal.  
4. Measured at 2.5 GHz with the triggering level adjusted for optimum trigger.  
5. High Sensitivity Hysteresis mode improves the high frequency trigger sensitivity but is not recommended when using noisy, low frequency signals that may  
result in false triggers without normal hysteresis enabled.  
6. Slew rate ≥ 2 V/ns.  
7. The Module Bay Trigger routes trigger signals from the module’s rear panel to the mainframe. 86100D-ETR is recommended when using a DCA module  
equipped with a rear-panel trigger circuit. Examples include 54754A, 83496x, and 86108A/B modules. If operating these modules in an 86100D with Option  
STR, an external cable (such as P/N 5062-6690) must be connected from the module’s front panel trigger/clock output to the 86100D’s trigger input.  
8. In precision timebase (PTB) operation with 750 mV input (500 mV input, 9 to 44 GHz).  
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