欢迎访问ic37.com |
会员登录 免费注册
发布采购

16861A-128 参数 Datasheet PDF下载

16861A-128图片预览
型号: 16861A-128
PDF下载: 下载PDF文件 查看货源
内容描述: [Portable Logic Analyzers]
分类和应用:
文件页数/大小: 22 页 / 2683 K
品牌: KEYSIGHT [ Keysight Technologies ]
 浏览型号16861A-128的Datasheet PDF文件第5页浏览型号16861A-128的Datasheet PDF文件第6页浏览型号16861A-128的Datasheet PDF文件第7页浏览型号16861A-128的Datasheet PDF文件第8页浏览型号16861A-128的Datasheet PDF文件第10页浏览型号16861A-128的Datasheet PDF文件第11页浏览型号16861A-128的Datasheet PDF文件第12页浏览型号16861A-128的Datasheet PDF文件第13页  
09 | Keysight | 16860A Series Portable Logic Analyzers - Data Sheet  
16860A Series Logic Analyzer Specifications and Characteristics (Continued)  
Timing (asynchronous) sampling mode  
Feature  
Full channel  
2.5 GHz  
400 ps to 10 ns  
Up to 128 M  
Half channel  
5.0 GHz  
200 ps  
Quarter channel (Optional on 16862A or 16864A, requires options -700 and –T10  
10 GHz  
100 ps  
Up to 512 M  
Max sample rate  
Sample period  
Memory depth  
Up to 256 M  
Timing mode functional characteristics  
Minimum data pulse width  
Timing interval accuracy  
Within a 16 channel pod  
Across 16 channel pods  
Maximum trigger sequencer speed  
Maximum trigger sequence steps  
Trigger sequence step branching  
Trigger position  
1 sample period + 200 ps  
± (1 sample period + 130 ps + 0.01% of time interval reading) 1  
± (1 sample period + 400 ps + 0.01% of time interval reading) 1  
2.5 GHz  
8
Arbitrary 4-way if/then/else  
Start, center, end or user-defined  
Trigger resources  
16 patterns evaluated as =, !=, >, >=, <, <=  
8 double-bounded ranges evaluated as in range, not in range  
4 edge detectors in timing, 3 in transitional timing  
1 occurrence counter per sequence level  
1 timer  
4 flags  
1 arm in  
Burst trigger  
2 event counters  
Arbitrary Boolean combinations  
Go to  
Trigger resource conditions  
Trigger actions  
Trigger and fill memory  
Trigger and go to  
Trigger, send e-mail and fill memory  
Occurrence counter reset  
Set  
Flag actions  
Clear  
Pulse set  
Pulse clear  
Maximum occurrence counter  
Maximum range width  
Maximum pattern width  
Timer range  
999,999,999  
64 bits  
128 bits single label  
200 sample clock period to 27 hours  
5 ns  
Timer resolution  
Timer accuracy  
Timer reset latency  
± (8 sample clock period + 2 ns + 0.01%)  
80 sample clock period  
Timing zoom (Captured simultaneously with timing or state sampling mode capture)  
Timing analysis sample rate  
Timing interval accuracy  
Within a 16 channel block  
Between 16 channel blocks  
Memory depth  
12.5 GHz (80 ps sample resolution)  
± (80 ps + 130 ps + 0.01% of time interval reading)  
± (80 ps + 400 ps + 0.01% of time interval reading)  
256 K samples  
Trigger position  
Minimum data pulse width  
Start, center, end or user-defined  
1 sample period + 200 ps  
1. With single-ended flying lead and Soft Touch Pro probes.