08 | Keysight | 16860A Series Portable Logic Analyzers - Data Sheet
16860A Series Logic Analyzer Specifications and Characteristics (Continued)
State mode functional characteristics
Single clock
Multiple clocks
Minimum setup time
80 ps
250 ps
Minimum hold time
80 ps
250 ps
Minimum data valid window
Sample position adjustment range
Sample position adjustment resolution
Minimum state clock pulse width
Clock qualifier setup time
160 ps
7 ns typical
20 ps typical
Single edge: 200 ps
500 ps
12 ns typical
80 ps typical
Single edge: 250 ps
200 ps
250 ps
Clock qualifier hold time
200 ps
250 ps
RESET clock qualifier setup time
RESET clock qualifier hold time
Minimum slave to master clock time
Minimum master to slave clock time
Minimum slave to slave clock time
Time tag resolution
2 ns
0 ps
N/A
N/A
N/A
80 ps
N/A
N/A
350 ps
150 ps
1.43 ns
80 ps
Maximum time count between stored states
Maximum trigger sequence steps
Trigger sequence step branching
Trigger position
66 days
8
66 days
16
Arbitrary 4-way if/then/else
Start, center, end or user-defined
– 16 patterns evaluated as =, !=, >,
>=, <, <=
– 8 double-bounded ranges
evaluated as in range, not in range
– 4 edge detectors in timing, 3 in
transitional timing
– 1 occurrence counter per sequence
level
Arbitrary 4-way if/then/else
Start, center, end or user-defined
– 16 patterns evaluated as =, !=, >, >=, <, <=
– 8 double-bounded ranges evaluated as in range, not in
range
– 4 edge detectors in timing, 3 in transitional timing
– 1 occurrence counter per sequence level
– 3 timers
Trigger resources
– 4 flags
– 1 arm in
– 1 timer
– Global counters - 2
– 4 flags
– 1 arm in
– Burst patterns
– Event counters - 2
999,999,999
64 bits
128 bits single label
200 sample clock period to 27 hours
5 ns
Maximum occurrence counter
Maximum range width
Maximum pattern width
Timer range
999,999,999
64 bits
128 bits single label
100 ns to 27 hours
5 ns
Timer resolution
Timer accuracy
Timer reset latency
± (8 sample clock period + 2 ns + 0.01%) ± (8 sample clock period + 2 ns + 0.01%)
80 sample clock period 80 sample clock period
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