07 | Keysight | 16860A Series Portable Logic Analyzers - Data Sheet
16860A Series Logic Analyzer Specifications and Characteristics
State (synchronous) sampling mode
16861A
16862A
16863A
16864A
Channels
34
68
102
(96 data and
6 clock)
136
(128 data and
8 clock)
(32 data and
2 clock)
(64 data and
4 clock)
Sampling option: Single clock
Clock (clock is on Pod 1)
Clock qualifiers
1
1
0
1
3
0
1
4
0
1
4
1
Reset qualifier
Sampling option: Multiple clocks
Clocks or clock qualifiers
Reset qualifier
2
0
4
0
4
0
4
0
Clock channels can be used as data channels.
The state sampling clock mode specifies how the clock inputs are used for sampling. The
availability of these state sampling clock modes depends on the state sampling option that you
select.
– Master - All pods sampled by the master clock definition.
–
–
In single clock mode, only the clock signal on Pod 1 can be used.
In multiple clocks, either a single clock signal can be used or a combination of clocks
can be used.
– Dual sample - In the dual sample clock mode, you can capture two samples per clock
edge with two different threshold offsets and separate sampling positions. These separate
threshold offsets and sampling positions allow you to set independent thresholds and
sampling positions for Read and Write in DDR/LPDDR captures and for Rising and Falling
edge in general-purpose data captures.
– Master/slave - Master pod is sampled on master clock and slave pod is sampled on slave
clock, but the captured data of both slave and master clocks is saved together when the
master clock occurs.
– Demux - Data being probed by one pod is demultiplexed into the logic analyzer memory
that is normally used for two pods. The demultiplex mode uses the master and slave clocks
to demultiplex the data.
350 MHz
(Base configuration)
700 MHz
(Option 700)
350 MHz
(Base configuration)
Sampling option
Available clock modes
Single clock
Master
Single clock
Master
Multiple clocks
Master
Dual sample
Dual sample
Master/slave
Demux
Maximum state data
rate (spec) 1
Captures data up to
Captures data up to
Captures data up to
350 Mbps on either edge 700 Mbps on either edge 700 Mbps on any
of a clock up to 350 MHz of the clock up to
700 MHz
combination of multiple
clocks up to 350 MHz
Captures data up to
Captures data up to
700 Mbps on both edges 1400 Mbps on both
of a clock up to 350 MHz edges of the clock up to
700 MHz
Maximum state clock
frequency
Minimum state clock
frequency
350 MHz
700 MHz
350 MHz
0 MHz
12.5 MHz (single edge),
6.25 MHz (both edges)
12.5 MHz (single edge),
6.25 MHz (both edges)
Minimum time between 1430 ps
active clock edges
715 ps
1430 ps
700 MHz
Maximum trigger
sequencer speed
700 MHz
1400 MHz
1. Specification (spec): Represents warranted performance of a calibrated instrument that has been stored for a
minimum of 2 hours within the operating temperature range of 5 to 40 °C, unless otherwise stated, and after
a 45-minute warm-up period. The specifications include measurement uncertainty.
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