KING BILLION ELECTRONICS CO., LTD
駿 億 電 子 股 份 有 限 公 司
HE83138
HE80000 SERIES
C. Pin Description
Pin # Pin name I/O Function
Description
External fast clock input/output
Mask Option setting:
78
77
B, pins are used to connect crystal or
O RC to generate the 32.768KHz ~
8MHz system clock.
MO_FCK/SCKN= 00 : Slow Clock only
01 : Illegal
FXI,
FXO
10：Dual Clock
11：Fast Clock only
MO_FOSCE= 0：Internal fast clock
1：External fast clock
MO_FXTAL= 0：R,C OSC. for Fast Clock
1：Crystal OSC. for Fast Clock
MO_SXTAL= 0：R,C OSC. for 32.768K Clock
External slow clock input/output
pins used to connect the
81
80
I, 32.768KHz crystal to generate
O slow clock for system operation
(slow mode), LCD display or
timer 1 clock source.
SXI,
SXO
1：Crystal OSC. for 32.768K Clock。
Use OP1 and OP2 to switch among different
operation mode (NORMAL, SLOW, IDEL and
SLEEP). In Dual Clock mode, the main system clock
is still the Fast Clock. The 32768 Hz clock is for LCD
and Timer 1 only.
Active low and level trigger reset signal. User can
also set the mask option MO_PORE=1 to enable the
build-in Power-on reset circuit besides using the reset
pin.
76
79
I
I
System reset signal
RSTP_N
Watch Dog Timer can also be enabled/disabled by the
mask option,
MO_WDTE = 0：Disable Watch Dog Timer
= 1：Enable Watch Dog Timer
Please bond this pin to ground by a 0 ohm
resistor to let it accessible when it’s necessary for
some testing.
IC Test Pin
TSTP_P
NC
91,92,
93,1
No Connection Pin
Bi-directional I/O port D. PRTD
Mask options setting:
MO_DPP [7:0] = 1：Push-pull output.
83:90
B [7:2] also used as wake-up pin,
and PRTD [7:6] also used as
external interrupt pin.
PRTD[7:0]
PRT17[7:0]
= 0：Open-drain output.
Output must be “1” before reading whenever uses
them as input (Non tri-state structure).
Mask options setting:
MO_17PP [7:0] = 1：Push-pull output.
12..19
B Bi-directional I/O port 17
= 0：Open-drain output.
Output must be “1” before reading whenever uses
them as input (Non tri-state structure).
11..4
LCD common/segment driving pins.
O LCD COM Output
O LCD SEG Output
COM[15:0]
SEG[31:0]
52..59
LCD Data filled from 80H; please refer the LCD
RAM map.
When LV3=VDD, the charge pump for LCD is turn off.
The capacitor between LC1 and LC2 shall be
removed to reduce power consumption.
20..51
61
60
B Charge Pump Switch 1
B Charge Pump Switch 2
LC2
LC1
63
62
B Charge Pump V3
B Charge Pump V1
LV3
LV1
Refer to application circuit.
2
V1.0
KB [ King blillion Electronics Co.,Ltd. ]
