®
IS62WV5128ALL, IS62WV5128BLL
ISSI
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)
55 ns
70 ns
Symbol
tWC
Parameter
Min. Max.
Min. Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Cycle Time
55
45
45
0
—
—
—
—
—
—
—
—
20
—
70
60
60
0
—
—
—
—
—
—
—
—
20
—
tSCS1
tAW
CS1 to Write End
Address Setup Time to Write End
Address Hold from Write End
Address Setup Time
WE Pulse Width
tHA
tSA
0
0
tPWE
tSD
40
25
0
50
30
0
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
tHD
(3)
tHZWE
—
5
—
5
(3)
tLZWE
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0.4V to
VDD-0.2V/VDD-0.3V and output loading specified in Figure 1.
2. The internal write time is defined by the overlap of CS1 LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to
terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write.
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
AC WAVEFORMS
WRITE CYCLE NO. 1 (CS1 Controlled, OE = HIGH or LOW)
t
WC
ADDRESS
t
HA
t
SCS1
CS1
t
AW
t
PWE
WE
DOUT
DIN
t
SA
t
HZWE
t
LZWE
HIGH-Z
SD
DATA UNDEFINED
t
t
HD
DATA-IN VALID
8
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
04/30/03
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
