IS61LV25616AL-10TLI 参数 Datasheet PDF下载

IS61LV25616AL

AC WAVEFORMS

WRITE CYCLE NO. 1

(CE Controlled, OE is HIGH or LOW)

(1 )

t

WC

ADDRESS

VALID ADDRESS

t

SA

CE

t

SCE

t

AW

t

PWE1

t

PWE2

t

PBW

t

HA

WE

UB, LB

t

HZWE

D

OUT

DATA UNDEFINED

HIGH-Z

t

LZWE

t

SD

D

IN

t

HD

DATA

IN

VALID

UB_CEWR1.eps

Notes:

1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CE and WE inputs and at least

one of the LB and UB inputs being in the LOW state.

2. WRITE = (CE)

[

(LB) = (UB)

]

(WE).

WRITE CYCLE NO. 2

(WE Controlled.

OE

is HIGH During Write Cycle)

(1,2)

t

WC

ADDRESS

VALID ADDRESS

t

HA

OE

CE

LOW

t

AW

WE

t

PWE1

t

PBW

t

SA

UB, LB

t

HZWE

D

OUT

DATA UNDEFINED

HIGH-Z

t

LZWE

t

SD

D

IN

t

HD

DATA

IN

VALID

UB_CEWR2.eps

Integrated Silicon Solution, Inc. — www.issi.com —

1-800-379-4774

Rev. F

12/15/2011

9