IS61LV256
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,3)
(Over Operating Range)
Symbol
Parameter
Write Cycle Time
-12 ns
Min. Max.
12
8
8
0
0
8
6
0
—
0
—
—
—
—
—
—
—
—
6
—
-15 ns
Min. Max.
15
10
10
0
0
10
8
0
—
0
—
—
—
—
—
—
—
—
7
—
-20 ns
Min. Max.
20
13
15
0
0
13
10
0
—
0
—
—
—
—
—
—
—
—
8
—
-25 ns
Min. Max.
25
15
20
0
0
15
12
0
—
0
—
—
—
—
—
—
—
—
10
—
ISSI
®
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
(4)
t
SD
t
HD
t
HZWE
(2)
t
LZWE
(2)
CE
to Write End
Address Setup Time to Write End
Address Hold from Write End
Address Setup Time
WE
Pulse Width
Data Setup to Write End
Data Hold from Write End
WE
LOW to High-Z Output
WE
HIGH to Low-Z Output
Notes:
1. Test conditions assume signal transition times of 3ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured
±500
mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of
CE
LOW and
WE
LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
4. Tested with
OE
HIGH.
AC WAVEFORMS
WRITE CYCLE NO. 1 (
WE
Controlled)
(1,2)
t
WC
ADDRESS
t
SCE
t
HA
CE
t
AW
WE
t
SA
t
HZWE
t
PWE
t
LZWE
HIGH-Z
D
OUT
DATA UNDEFINED
t
SD
t
HD
D
IN
DATA-IN VALID
2-6
Integrated Silicon Solution, Inc.
Rev. F 0296
SR81995LV61
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
