®
IS42S32400B
ISSI
CLOCK SUSPEND
Any command or data present on the input pins at the time
of a suspended internal clock edge is ignored; any data
presentontheDQpinsremainsdriven;andburstcounters
are not incremented, as long as the clock is suspended.
(Seefollowingexamples.)
Clock suspend mode occurs when a column access/burst
is in progress and CKE is registered LOW. In the clock
suspend mode, the internal clock is deactivated, “freezing”
the synchronous logic.
For each positive clock edge on which CKE is sampled
LOW, the next internal positive clock edge is suspended.
ClocksuspendmodeisexitedbyregisteringCKEHIGH;the
internal clock and related operation will resume on the
subsequent positive clock edge.
Clock Suspend During WRITE Burst
T0
T1
T2
T3
T4
T5
CLK
CKE
INTERNAL
CLOCK
COMMAND
ADDRESS
DQ
NOP
WRITE
NOP
NOP
BANK a,
COL n
DIN
n
DIN n+1
DIN n+2
DON'T CARE
Clock Suspend During READ Burst
T0
T1
T2
T3
T4
T5
T6
CLK
CKE
INTERNAL
CLOCK
COMMAND
ADDRESS
DQ
READ
NOP
NOP
NOP
NOP
NOP
BANK a,
COL n
DOUT
n
D
OUT n+1
DOUT n+2
D
OUT n+3
DON'T CARE
44
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00G
06/15/06
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
