IS42S81600D, IS42S16800D
WRITE with Auto Precharge
4.InterruptedbyaWRITE(withorwithoutautoprecharge):
WRITE to bank m will interrupt a WRITE on bank n when
3. Interrupted by a READ (with or without auto precharge):
AREADtobankmwillinterruptaWRITEonbanknwhen
registered,withthedata-outappearing(CASlatency) later.
The PRECHARGE to bank n will begin after tDPL is met,
wheretDPL beginswhentheREADtobankmisregistered.
ThelastvalidWRITEtobanknwillbedata-inregisteredone
clock prior to the READ to bank m.
A
registered. The PRECHARGE to bank n will begin after
tDPL ismet,wheretDPL beginswhentheWRITEtobankm
is registered. The last valid data WRITE to bank n will be
data registered one clock prior to a WRITE to bank m.
WRITE With Auto Precharge interrupted by a READ
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
BANK n
WRITE - AP
BANK n
READ - AP
BANK m
NOP
NOP
NOP
NOP
NOP
NOP
Page Active
WRITE with Burst of 4 Interrupt Burst, Write-Back
DPL - BANK n
Precharge
t
tRP - BANK n
Internal States
tRP - BANK m
BANK m
Page Active
READ with Burst of 4
Precharge
BANK n,
COL a
BANK m,
COL b
ADDRESS
DQ
D
IN
a
DIN a+1
DOUT
b
DOUT b+1
CAS Latency - 3 (BANK m)
DON'T CARE
WRITE With Auto Precharge interrupted by a WRITE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
BANK n
WRITE - AP
BANK n
WRITE - AP
BANK m
NOP
NOP
NOP
NOP
NOP
NOP
Page Active
WRITE with Burst of 4
Interrupt Burst, Write-Back
DPL - BANK n
Precharge
t
t
RP - BANK n
Internal States
tDPL - BANK m
BANK m
Page Active
WRITE with Burst of 4
Write-Back
BANK n,
COL a
BANK m,
COL b
ADDRESS
DQ
D
IN
a
DIN a+1
DIN a+2
D
IN
b
DIN b+1
DIN b+2
DIN b+3
DON'T CARE
50
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
07/28/08
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
