IS42S83200B, IS42S16160B
FUNCTIONAL TRUTH TABLE Continued:
Current State
CS
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
RAS CAS WE
Address
Command
DESL
Action
Write Recovering
×
H
H
H
H
L
×
H
H
L
×
H
L
×
Nop, Enter row active after tDPL
Nop, Enter row active after tDPL
Nop, Enter row active after tDPL
Begin read (8)
×
NOP
×
BST
H
L
BA, CA, A10
READ/READA
WRIT/WRITA
ACT
L
BA, CA, A10
Begin new write
ILLEGAL (3)
ILLEGAL (3)
H
H
L
H
L
BA, RA
L
BA, A10
PRE/PALL
REF/SELF
MRS
L
H
L
×
ILLEGAL
L
L
OC, BA
ILLEGAL
Write Recovering
with Auto
×
×
H
H
L
×
H
L
×
DESL
Nop, Enter precharge after tDPL
Nop, Enter precharge after tDPL
Nop, Enter row active after tDPL
ILLEGAL(3,8,11)
ILLEGAL (3,11)
ILLEGAL (3,11)
H
H
H
H
L
×
NOP
Precharge
×
BST
H
L
BA, CA, A10
READ/READA
WRIT/WRITA
ACT
L
BA, CA, A10
H
H
L
H
L
BA, RA
L
BA, A10
PRE/PALL
REF/SELF
MRS
ILLEGAL (3,11)
L
H
L
×
ILLEGAL
L
L
OC, BA
ILLEGAL
Refresh
×
×
H
L
×
×
H
L
×
DESL
Nop, Enter idle after tRC
Nop, Enter idle after tRC
ILLEGAL
H
H
H
L
×
NOP/BST
READ/READA
WRIT/WRITA
ACT
BA, CA, A10
L
BA, CA, A10
ILLEGAL
H
H
L
H
L
BA, RA
ILLEGAL
L
BA, A10
PRE/PALL
REF/SELF
MRS
ILLEGAL
L
H
L
×
ILLEGAL
L
L
OC, BA
ILLEGAL
Mode Register
Accessing
×
×
H
H
L
×
H
L
×
DESL
Nop, Enter idle after 2 clocks
Nop, Enter idle after 2 clocks
ILLEGAL
H
H
H
L
×
NOP
×
BST
×
×
BA, CA, A10
BA, RA
READ/WRITE
ILLEGAL
×
ACT/PRE/PALL ILLEGAL
REF/MRS
Note: H=VIH, L=VIL x= VIH or VIL, V = Valid Data, BA= Bank Address, CA+Column Address, RA=Row Address, OC= Op-Code
Notes:
1. All entries assume that CKE is active (CKEn-1=CKEn=H).
2. If both banks are idle, and CKE is inactive (Low), the device will enter Power Down mode. All input buffers except CKE will
be disabled.
3. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA), depending on the
state of that bank.
4. If both banks are idle, and CKE is inactive (Low), the device will enter Self-Refresh mode. All input buffers except CKE will
be disabled.
5. Illegal if tRCD is not satisfied.
6. Illegal if tRAS is not satisfied.
7. Must satisfy burst interrupt condition.
8. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
9. Must mask preceding data which don’t satisfy tDPL.
10. Illegal if tRRD is not satisfied.
11. Illegal for single bank, but legal for other banks.
12
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
07/28/08
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
