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IC41C16256-50KIG 参数 Datasheet PDF下载

IC41C16256-50KIG图片预览
型号: IC41C16256-50KIG
PDF下载: 下载PDF文件 查看货源
内容描述: [EDO DRAM, 256KX16, 50ns, CMOS, PDSO40, 0.400 INCH, LEAD FREE, SOJ-40]
分类和应用: 动态存储器光电二极管内存集成电路
文件页数/大小: 21 页 / 209 K
品牌: ISSI [ INTEGRATED SILICON SOLUTION, INC ]
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IC41C16256  
IC41LV16256  
AC CHARACTERISTICS (Continued)(1,2,3,4,5,6)  
(Recommended Operating Conditions unless otherwise noted.)  
-25  
-35  
-50  
-60  
Symbol  
Parameter  
Min. Max. Min. Max.  
Min. Max. Min. Max. Units  
tACH  
Column-Address Setup Time to CAS  
15  
15  
15  
10  
15  
15  
ns  
ns  
Precharge during WRITE Cycle  
tOEH  
OE Hold Time from WE during  
5
8
READ-MODIFY-WRITE cycle(18)  
tDS  
tDH  
tRWC  
tRWD  
Data-In Setup Time(15, 22)  
0
5
65  
35  
0
6
80  
45  
0
8
125  
70  
0
10  
140  
80  
ns  
ns  
ns  
ns  
Data-In Hold Time(15, 22)  
READ-MODIFY-WRITE Cycle Time  
RAS to WE Delay Time during  
READ-MODIFY-WRITE Cycle(14)  
tCWD  
tAWD  
tPC  
CAS to WE Delay Time(14, 20)  
17  
21  
10  
25  
30  
12  
34  
42  
20  
36  
49  
25  
ns  
ns  
ns  
Column-Address to WE Delay Time(14)  
EDO Page Mode READ or WRITE  
Cycle Time(24)  
tRASP  
tCPA  
tPRWC  
RAS Pulse Width in EDO Page Mode  
Access Time from CAS Precharge(15)  
25 100K 35 100K  
32  
50 100K  
47  
50 100K ns  
56  
14  
40  
21  
27  
34  
ns  
ns  
EDO Page Mode READ-WRITE  
Cycle Time(24)  
tCOH  
tOFF  
Data Output Hold after CAS LOW  
Output Buffer Turn-Off Delay from  
5
3
15  
5
3
15  
5
3
15  
5
3
15  
ns  
ns  
(13,15,19, 29)  
CAS or RAS  
tWHZ  
tCLCH  
Output Disable Delay from WE  
3
10  
15  
3
10  
15  
3
10  
15  
3
10  
15  
ns  
ns  
Last CAS going LOW to First CAS  
returning HIGH(23)  
tCSR  
tCHR  
tORD  
CAS Setup Time (CBR REFRESH)(30, 20)  
5
7
0
8
8
0
10  
10  
0
10  
10  
0
ns  
ns  
ns  
CAS Hold Time (CBR REFRESH)(30, 21)  
OE Setup Time prior to RAS during  
HIDDEN REFRESH Cycle  
tREF  
tT  
Refresh Period (512 Cycles)  
1
8
50  
1
8
50  
8
1
50  
8
1
50  
ms  
ns  
Transition Time (Rise or Fall)(2, 3)  
AC TEST CONDITIONS  
Output load:  
Two TTL Loads and 50 pF (Vcc = 5.0V ±10%)  
One TTL Load and 50 pF (Vcc = 3.3V ±10%)  
Input timing reference levels: VIH = 2.4V, VIL = 0.8V (Vcc = 5.0V ±10%);  
VIH = 2.0V, VIL = 0.8V (Vcc = 3.3V ±10%)  
Output timing reference levels: VOH = 2.0V, VOL = 0.8V (Vcc = 5V ±10%, 3.3V ±10%)  
Integrated Circuit Solution Inc.  
9
DR018-0C 04/23/2004  
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