IC41C16256
IC41LV16256
ELECTRICAL CHARACTERISTICS(1)
(Recommended Operating Conditions unless otherwise noted.)
Symbol Parameter
TestCondition
Speed Min.
Max.
Unit
IIL
Input Leakage Current
Any input 0V < VIN < Vcc
–10
10
µA
Other inputs not under test = 0V
IIO
Output Leakage Current
Output is disabled (Hi-Z)
0V < VOUT < Vcc
–10
10
µA
VOH
VOL
ICC1
Output High Voltage Level
Output Low Voltage Level
Standby Current: TTL
IOH = –2.5 mA
IOL =+2.1mA
2.4
—
—
V
V
0.4
RAS, LCAS, UCAS > VIH Commerical 5V
Industrial 5V
—
—
—
—
2
3
1
2
mA
Commerical 3.3V
Industrial
RAS, LCAS, UCAS > VCC – 0.2V
3.3V
ICC2
ICC3
Standby Current: CMOS
5V
—
—
1
mA
mA
3.3V
0.5
Operating Current:
RAS, LCAS, UCAS,
-25
-35
-50
-60
—
—
—
—
260
230
180
170
Random Read/Write(2,3,4)
Average Power Supply Current
Address Cycling, tRC = tRC (min.)
ICC4
ICC5
ICC6
Operating Current:
RAS = VIL, LCAS, UCAS,
-25
-35
-50
-60
—
—
—
—
250
220
170
160
mA
mA
mA
EDO Page Mode(2,3,4)
Cycling tPC = tPC (min.)
Average Power Supply Current
Refresh Current:
RAS Cycling, LCAS, UCAS > VIH
-25
-35
-50
-60
—
—
—
—
260
230
180
170
RAS-Only(2,3)
tRC = tRC (min.)
Average Power Supply Current
Refresh Current:
RAS, LCAS, UCAS Cycling
-25
-35
-50
-60
—
—
—
—
260
230
180
170
CBR(2,3,5)
tRC = tRC (min.)
Average Power Supply Current
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each EDO page cycle.
5. Enables on-chip refresh and address counters.
Integrated Circuit Solution Inc.
7
DR018-0C 04/23/2004
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
