欢迎访问ic37.com |
会员登录 免费注册
发布采购

IC41LV8512-60K 参数 Datasheet PDF下载

IC41LV8512-60K图片预览
型号: IC41LV8512-60K
PDF下载: 下载PDF文件 查看货源
内容描述: [EDO DRAM, 512KX8, 60ns, CMOS, PDSO28, 0.400 INCH, SOJ-28]
分类和应用: 动态存储器光电二极管内存集成电路
文件页数/大小: 21 页 / 202 K
品牌: ISSI [ INTEGRATED SILICON SOLUTION, INC ]
 浏览型号IC41LV8512-60K的Datasheet PDF文件第3页浏览型号IC41LV8512-60K的Datasheet PDF文件第4页浏览型号IC41LV8512-60K的Datasheet PDF文件第5页浏览型号IC41LV8512-60K的Datasheet PDF文件第6页浏览型号IC41LV8512-60K的Datasheet PDF文件第8页浏览型号IC41LV8512-60K的Datasheet PDF文件第9页浏览型号IC41LV8512-60K的Datasheet PDF文件第10页浏览型号IC41LV8512-60K的Datasheet PDF文件第11页  
IC41C8512  
IC41LV8512  
ELECTRICAL CHARACTERISTICS(1)  
(Recommended Operating Conditions unless otherwise noted.)  
Symbol Parameter  
Test Condition  
Speed Min. Max.  
Unit  
IIL  
Input Leakage Current  
Any input 0V VIN Vcc  
–10  
10  
µA  
Other inputs not under test = 0V  
IIO  
Output Leakage Current  
Output is disabled (Hi-Z)  
–10  
10  
µA  
0V VOUT Vcc  
VOH  
VOL  
ICC1  
Output High Voltage Level  
Output Low Voltage Level  
Standby Current: TTL  
IOH = –2.5 mA  
IOL =+2.1mA  
2.4  
V
V
0.4  
RAS, CAS VIH  
5V  
3.3V  
2
0.5  
mA  
ICC2  
ICC3  
Standby Current: CMOS  
RAS, CAS VCC – 0.2V  
5V  
3.3V  
1
0.5  
mA  
mA  
OperatingCurrent:  
RAS, CAS,  
Address Cycling, tRC = tRC (min.)  
-35  
-50  
-60  
120  
110  
100  
RandomRead/Write(2,3,4)  
Average Power Supply Current  
ICC4  
ICC5  
ICC6  
OperatingCurrent:  
RAS = VIL, CAS,  
-35  
-50  
-60  
100  
90  
80  
mA  
mA  
mA  
EDO Page Mode(2,3,4)  
Cycling tPC = tPC (min.)  
Average Power Supply Current  
Refresh Current:  
RAS Cycling, CAS VIH  
tRC = tRC (min.)  
-35  
-50  
-60  
120  
110  
100  
RAS-Only(2,3)  
Average Power Supply Current  
Refresh Current:  
RAS, CAS Cycling  
tRC = tRC (min.)  
-35  
-50  
-60  
120  
110  
100  
CBR(2,3,5)  
Average Power Supply Current  
Notes:  
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device  
operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.  
2. Dependent on cycle rates.  
3. Specified values are obtained with minimum cycle time and the output open.  
4. Column-address is changed once each EDO page cycle.  
5. Enables on-chip refresh and address counters.  
Integrated Circuit Solution Inc.  
DR029-0A 09/28/2001  
7