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IC41C44052-60TI 参数 Datasheet PDF下载

IC41C44052-60TI图片预览
型号: IC41C44052-60TI
PDF下载: 下载PDF文件 查看货源
内容描述: [Fast Page DRAM, 4MX4, 60ns, CMOS, PDSO24,]
分类和应用: 动态存储器光电二极管内存集成电路
文件页数/大小: 18 页 / 205 K
品牌: ISSI [ INTEGRATED SILICON SOLUTION, INC ]
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IC41C4405x and IC41LV4405x Series  
FunctionalDescription  
Refresh Cycle  
The IC41C4405x and IC41LV4405x are CMOS DRAMs  
optimized for high-speed bandwidth, low power  
applications. During READ or WRITE cycles, each bit is  
uniquely addressed through the 11 or 12 address bits.  
These are entered 11 bits (A0-A10) at a time for the 2K  
refresh device or 12 bits (A0-A11) at a time for the 4K  
refresh device. The row address is latched by the Row  
Address Strobe (RAS). The column address is latched by  
the Column Address Strobe (CAS). RAS is used to latch  
the first nine bits and CAS is used the latter ten bits.  
To retain data, 2,048 refresh cycles are required in each  
32 ms period, or 4,096 refresh cycles are required in each  
64ms period. There are two ways to refresh the memory:  
1. By clocking each of the 2,048 row addresses (A0  
through A10) or 4096 row addresses (A0 through A11)  
with RAS at least once every 32 ms or 64ms respectively.  
Any read, write, read-modify-write or RAS-only cycle  
refreshes the addressed row.  
2. Using a CAS-before-RAS refresh cycle. CAS-before-  
RAS refresh is activated by the falling edge of RAS,  
while holding CAS LOW. In CAS-before-RAS refresh  
cycle, an internal 11(12)-bit counter provides the row  
addresses and the external address inputs are ignored.  
Memory Cycle  
A memory cycle is initiated by bring RAS LOW and it is  
terminated by returning both RAS and CAS HIGH. To  
ensures proper device operation and data integrity any  
memory cycle, once initiated, must not be ended or  
aborted before the minimum tRAS time has expired. A new  
cycle must not be initiated until the minimum precharge  
time tRP, tCP has elapsed.  
CAS-before-RAS is a refresh-only mode and no data  
access or device selection is allowed. Thus, the output  
remains in the High-Z state during the cycle.  
Power-On  
Read Cycle  
After application of the VCC supply, an initial pause of  
200 µs is required followed by a minimum of eight initial-  
ization cycles (any combination of cycles containing a  
RAS signal).  
A read cycle is initiated by the falling edge of CAS or OE,  
whichever occurs last, while holding WE HIGH. The  
column address must be held for a minimum time specified  
by tAR. Data Out becomes valid only when tRAC, tAA, tCAC  
and tOEA are all satisfied. As a result, the access time is  
dependent on the timing relationships between these  
parameters.  
During power-on, it is recommended that RAS track with  
VCC or be held at a valid VIH to avoid current surges.  
Write Cycle  
A write cycle is initiated by the falling edge of CAS and WE,  
whichever occurs last. The input data must be valid at or  
before the falling edge of CAS or WE, whichever occurs  
last.  
4
Integrated Circuit Solution Inc.  
DR013-0B 10/17/2002  
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