AS7C33512PFS16A-150BI 参数 Datasheet PDF下载

AS7C33512PFS16A

AS7C33512PFS18A

®

Signal descriptions

Signal

CLK

A0–A18

DQ[a,b]

CE0

CE1, CE2

ADSP

ADSC

ADV

GWE

BWE

BW[a,b]

OE

LBO

I/O

I

I

I/O

I

I

I

I

I

I

I

I

I

I

I

I

Properties

CLOCK

SYNC

SYNC

SYNC

SYNC

SYNC

SYNC

SYNC

SYNC

SYNC

SYNC

ASYNC

STATIC

STATIC

ASYNC

Description

Clock. All inputs except OE,

FT

, ZZ,

LBO

are synchronous to this clock.

Address. Sampled when all chip enables are active and ADSC or ADSP are asserted.

Data. Driven as output when the chip is enabled and OE is active.

Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When

CE0 is inactive, ADSP is blocked. Refer to the Synchronous Truth Table for more

information.

Synchronous chip enables. Active HIGH and active LOW, respectively. Sampled on

clock edges when ADSC is active or when CE0 and ADSP are active.

Address strobe (processor). Asserted LOW to load a new address or to enter standby

mode.

Address strobe (controller). Asserted LOW to load a new address or to enter standby

mode.

Burst advance. Asserted LOW to continue burst read/write.

Global write enable. Asserted LOW to write all 16/18 bits. When HIGH, BWE and

BW[a,b] control write enable.

Byte write enable. Asserted LOW with GWE = HIGH to enable effect of BW[a,b]

inputs.

Write enables. Used to control write of individual bytes when GWE = HIGH and

BWE = LOW. If any of BW[a,b] is active with GWE = HIGH and BWE = LOW the

cycle is a write cycle. If all BW[a,b] are inactive, the cycle is a read cycle.

Asynchronous output enable. I/O pins are driven when OE is active and the chip is

in read mode.

Count mode. When driven HIGH, count sequence follows Intel XOR convention.

When driven LOW, count sequence follows linear convention. This signal is

internally pulled HIGH.

Flow-through mode.When LOW, enables single register flow-through mode.

Connect to V

DD

if unused or for pipelined operation.

Snooze. Places device in low power mode; data is retained. Connect to GND if

unused.

FT

ZZ

Absolute maximum ratings

Parameter

Power supply voltage relative to GND

Input voltage relative to GND (input pins)

Input voltage relative to GND (I/O pins)

Power dissipation

DC output current

Storage temperature (plastic)

Temperature under bias

Symbol

V

DD

, V

DDQ

V

IN

V

IN

P

D

I

OUT

T

stg

T

bias

Min

–0.5

–0.5

–0.5

–

–

–65

–65

Max

+4.6

V

DD

+ 0.5

V

DDQ

+ 0.5

1.8

50

+150

+135

Unit

V

V

V

W

mA

°

C

°

C

Note: Stresses greater than those listed under

Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress rating only and functional opera-

tion of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions may affect reliability.

4/15/02; v.1.5

Alliance Semiconductor

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