April 2002
Preliminary
®
AS7C33512PFS16A
AS7C33512PFS18A
3.3V 512K
×
16/18 pipeline burst synchronous SRAM
Features
•
•
•
•
•
•
•
Organization: 524,288 words × 16 or 18 bits
Fast clock speeds to 166 MHz in LVTTL/LVCMOS
Fast clock to data access: 3.5/3.8/4.0/5.0 ns
Fast OE access time: 3.5/3.8/4.0/5.0 ns
Fully synchronous register-to-register operation
Single register “Flow-through” option
Single-cycle deselect
- Dual-cycle deselect also available (AS7C33512PFD16A/
AS7C33512PFD18A)
• Available in both 2 chip enable and 3 chip enable
- 2 CE part number is AS7C33512PFS16A or AS7C33512PFS18A2
• Asynchronous output enable control
• Available in 100-pin TQFP and 119-ball BGA package
• Byte write enables
• Multiple chip enables for easy expansion
• 3.3V core power supply
• 2.5V or 3.3V I/O operation with separate V
DDQ
• 30 mW typical standby power in power down mode
• NTD™
pipeline architecture available
(AS7C33512NTD16A/AS7C33512NTD18A)
1. Pentium
®
is a registered trademark of Intel Corporation. NTD™ is a
trademark of Alliance Semiconductor Corporation. All trademarks men-
tioned in this document are the property of their respective owners.
• Pentium®
1
compatible architecture and timing
Logic block diagram
LBO
CLK
ADV
ADSC
ADSP
A[18:0]
CLK
CS
CLR
Burst logic
Q
19
D
CS
CLK
19
17 19
Address
register
512K × 16/18
Memory
array
16/18 16/18
GWE
BW
b
BWE
BW
a
CE0
CE1
CE2
D
DQb
Q
Byte Write
registers
Byte Write
registers
CLK
D
CLK
D
DQa
Q
2
OE
Enable
Q
register
CE
CLK
ZZ
Output
registers
CLK
Input
registers
CLK
Power
down
D
Enable
Q
delay
register
CLK
OE
16/18
FT
DQ[a,b]
Selection guide
–166
Minimum cycle time
Maximum pipelined clock frequency
Maximum pipelined clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
6
166
3.5
475
130
30
–150
6.6
150
3.8
450
110
30
–133
7.5
133
4
425
100
30
–100
10
100
5
325
90
30
Units
ns
MHz
ns
mA
mA
mA
4/15/02;
v.1.5
Alliance Semiconductor
1 of 14
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