AS7C332MNTD18A
®
Signal descriptions
Signal
CLK
CEN
A, A0, A1
DQ[a,b]
CE0, CE1,
CE2
ADV/LD
R/W
BW[a,b]
OE
LBO
FT
TDO
TDI
TMS
TCK
ZZ
NC
I/O
I
I
I
I/O
I
I
I
I
I
I
I
O
I
I
O
I
-
Properties Description
CLOCK
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
ASYNC
STATIC
STATIC
SYNC
SYNC
SYNC
SYNC
ASYNC
-
Clock. All inputs except OE, FT, LBO, and ZZ are synchronous to this clock.
Clock enable. When de-asserted high, the clock input signal is masked.
Address. Sampled when all chip enables are active and ADV/LD is asserted.
Data. Driven as output when the chip is enabled and OE is active.
Synchronous chip enables. Sampled at the rising edge of CLK, when ADV/LD is asserted.
Are ignored when ADV/LD is high.
Advance or Load. When sampled high, the internal burst address counter will increment in
the order defined by the LBO input value. (refer to table on page 2) When low, a new
address is loaded.
A high during LOAD initiates a READ operation. A low during LOAD initiates a WRITE
operation. Is ignored when ADV/LD is high.
Byte write enables. Used to control write on individual bytes. Sampled along with WRITE
command and BURST WRITE.
Asynchronous output enable. I/O pins are not driven when OE is inactive.
Selects Burst mode. When tied to V
DD
or left floating, device follows interleaved Burst order. When
driven Low, device follows linear Burst order.
This signal is internally pulled High.
Selects Pipeline or Flow-through mode. When tied to V
DD
or left floating, enables Pipeline mode.
When driven Low, enables single register Flow-through mode.
This signal is internally pulled High.
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. (BGA
only)
Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. (BGA only)
This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK.
(BGA only)
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. (BGA
only)
Snooze. Places device in low power mode; data is retained. Connect to GND if unused.
No connects.
4/26/04, V 1.2
Alliance Semiconductor
P. 5 of 22
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
