April 2004
®
AS7C332MNTD18A
3.3V 2M × 18 SRAM with NTD
TM
Features
• Organization: 2,097,152 words × 18 bits
• NTD
™1
architecture for efficient bus operation
• Fast clock speeds to 200 MHz in LVTTL/LVCMOS
• Fast clock to data access: 3.1/3.4/3.8 ns
• Fast OE access time: 3.1/3.4/3.8 ns
• Fully synchronous operation
• Flow-through or pipelined mode
1. NTD™ is a trademark of Alliance Semiconductor Corporation. All trade-
marks mentioned in this document are the property of their respective owners.
• Common data inputs and data outputs
• Asynchronous output enable control
• Available in 100-pin TQFP and 165-ball BGA packages
• Byte write enables
• Clock enable for operation hold
• Multiple chip enables for easy expansion
• 3.3V core power supply
• 2.5V or 3.3V I/O operation with separate V
DDQ
• Self-timed write cycles
• Interleaved or linear burst modes
• Snooze mode for standby operation
• Boundary scan using IEEE 1149.1 JTAG function
21
Logic block diagram
A[20:0]
21
D
Address
register
Burst logic
Q
CLK
CE0
CE1
CE2
R/W
BWa
BWb
ADV / LD
FT
LBO
ZZ
CLK
D
Q
21
Write delay
addr. registers
CLK
Control
logic
CLK
Write Buffer
2 M x 18
SRAM
Array
DQ[a,b]
18
D
Data
Q
Input
Register
CLK
18
18
18
18
CLK
CEN
CLK
OE
Output
Register
18
OE
DQ[a,b]
Selection guide
-200
Minimum cycle time
Maximum pipelined clock frequency
Maximum pipelined clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
4/26/04, V 1.2
-167
6
167
3.4
350
110
70
-133
7.5
133
3.8
325
100
70
Units
ns
MHz
ns
mA
mA
mA
P. 1 of 22
5
200
3.1
400
120
70
Alliance Semiconductor
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