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AS7C33256PFS36A-100BC 参数 Datasheet PDF下载

AS7C33256PFS36A-100BC图片预览
型号: AS7C33256PFS36A-100BC
PDF下载: 下载PDF文件 查看货源
内容描述: [Standard SRAM, 256KX36, 12ns, CMOS, PBGA119, 14 X 20 MM, BGA-119]
分类和应用: 静态存储器内存集成电路
文件页数/大小: 14 页 / 384 K
品牌: ISSI [ INTEGRATED SILICON SOLUTION, INC ]
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AS7C33256PFS32A  
AS7C33256PFS36A  
®
Timing characteristics over operating range  
–166  
–150  
–133  
–100  
Parameter  
Symbol Min Max Min Max Min Max Min Max Unit Notes1  
Clock frequency  
fMax  
tCYC  
6
166  
150  
133  
100 MHz  
Cycle time (pipelined mode)  
6.6  
10  
-
7.5  
12  
-
10  
12  
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Cycle time (flow-through mode)  
tCYCF  
10  
-
Clock access time (pipelined mode)- 3.3V VDDQ tCD 3.3V  
Clock access time (pipelined mode)- 2.5V VDDQ tCD 2.5V  
3.5  
4.0  
9
3.8  
4.3  
10  
3.8  
4.0  
4.5  
10  
4.0  
5.0  
5.0  
12  
5.0  
-
-
-
-
Clock access time (flow-through mode)  
Output enable LOW to data valid  
Clock HIGH to output Low Z  
Data output invalid from clock HIGH  
Output enable LOW to output Low Z  
Output enable HIGH to output High Z  
Clock HIGH to output High Z  
Output enable HIGH to invalid output  
Clock HIGH pulse width  
tCDF  
tOE  
tLZC  
tOH  
3.5  
0
0
0
0
2,3,4  
2
1.5  
0
1.5  
0
1.5  
0
1.5  
0
tLZOE  
tHZOE  
tHZC  
tOHOE  
tCH  
2,3,4  
2,3,4  
2,3,4  
3.5  
3.5  
3.8  
3.8  
4.0  
4.0  
4.5  
5.0  
0
0
0
0
2.4  
2.4  
1.5  
1.5  
1.5  
1.5  
0.5  
0.5  
0.5  
0.5  
1.5  
2.5  
2.5  
1.5  
1.5  
1.5  
1.5  
0.5  
0.5  
0.5  
0.5  
1.5  
1.5  
1.5  
0.5  
0.5  
0.5  
2.5  
2.5  
1.5  
1.5  
1.5  
1.5  
0.5  
0.5  
0.5  
0.5  
1.5  
1.5  
1.5  
0.5  
0.5  
0.5  
3.5  
3.5  
2.0  
2.0  
2.0  
2.0  
0.5  
0.5  
0.5  
0.5  
2.0  
2.0  
2.0  
0.5  
0.5  
0.5  
5
5
Clock LOW pulse width  
tCL  
Address setup to clock HIGH  
Data setup to clock HIGH  
tAS  
6
tDS  
6
Write setup to clock HIGH  
tWS  
6,7  
6,8  
6
Chip select setup to clock HIGH  
Address hold from clock HIGH  
Data hold from clock HIGH  
Write hold from clock HIGH  
Chip select hold from clock HIGH  
ADV setup to clock HIGH  
tCSS  
tAH  
tDH  
6
tWH  
tCSH  
tADVS  
6,7  
6,8  
6
ADSP setup to clock HIGH  
tADSPS 1.5  
tADSCS 1.5  
tADVH 0.5  
tADSPH 0.5  
tADSCH 0.5  
6
ADSC setup to clock HIGH  
6
ADV hold from clock HIGH  
ADSP hold from clock HIGH  
ADSC hold from clock HIGH  
1 See “Notes” on page 12  
6
6
6
4/15/02; v.1.9  
Alliance Semiconductor  
P. 8 of 14  
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