April 2002
Preliminary
®
AS7C33256PFS32A
AS7C33256PFS36A
3.3V 256K
×
32/36 pipeline burst synchronous SRAM
Features
•
•
•
•
•
•
•
Organization: 262,144 words x 32 or 36 bits
Fast clock speeds to 166 MHz in LVTTL/LVCMOS
Fast clock to data access: 3.5/3.8/4.0/5.0 ns
Fast OE access time: 3.5/3.8/4.0/5.0 ns
Fully synchronous register-to-register operation
Single register “Flow-through” option
Single-cycle deselect
- Dual-cycle deselect also available (AS7C33256PFD32A/
AS7C33256PFD36A)
• Available in both 2 chip enable and 3 chip enable
- 2 CE part number is AS7C33256PFS32A2 or AS7C33256PFS36A2
•
•
•
•
•
•
•
•
Pentium®
1
compatible architecture and timing
Asynchronous output enable control
Available in100-pin TQFP and 119-pin BGA packages
Byte write enables
3.3V core power supply
2.5V or 3.3V I/O operation with separate V
DDQ
30 mW typical standby power in power down mode
NTD™
1
pipeline architecture available
(AS7C33256NTD32A/ AS7C33256NTD36A)
Logic block diagram
LBO
CLK
ADV
ADSC
ADSP
A[17:0]
1 Pentium
®
is a registered trademark of Intel Corporation. NTD™ is a
trademark of Alliance Semiconductor Corporation. All trademarks
mentioned in this document are the property of their respective
owners.
CLK
CE
CLR
18
D
Address
CE
register
CLK
D
Q0
Burst logic
Q1
18
Q
16
18
256K × 32/36
Memory
array
BWE
GWE
BW
d
DQ
d
Q
Byte write
registers
CLK
DQ
c
Q
Byte write
registers
CLK
D
DQ
b
Q
Byte write
registers
CLK
DQ
a
Q
Byte write
registers
CLK
D
Enable
CE
register
CLK
Power
down
D
Enable
Q
delay
register
CLK
Q
D
D
36/32
36/32
BW
c
BW
b
BW
a
CE0
CE1
CE2
4
OE
Output
registers
CLK
Input
registers
CLK
ZZ
OE
FT
36/32
DQ[a:d]
Selection guide
–166
Minimum cycle time
Maximum pipelined clock frequency
Maximum pipelined clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
6
166
3.5
475
130
30
–150
6.6
150
3.8
450
110
30
–133
7.5
133
4
425
100
30
–100
10
100
5
325
90
30
Units
ns
MHz
ns
mA
mA
mA
4/15/02; v.1.9
Alliance Semiconductor
P. 1 of 14
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