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AS7C33256PFD18B-200TQIN 参数 Datasheet PDF下载

AS7C33256PFD18B-200TQIN图片预览
型号: AS7C33256PFD18B-200TQIN
PDF下载: 下载PDF文件 查看货源
内容描述: [Standard SRAM, 256KX18, 3ns, CMOS, PQFP100, 14 X 20 MM, LEAD FREE, TQFP-100]
分类和应用: 静态存储器内存集成电路
文件页数/大小: 19 页 / 536 K
品牌: ISSI [ INTEGRATED SILICON SOLUTION, INC ]
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AS7C33256PFD18B  
®
Write enable truth table (per byte)  
Function  
GWE BWE  
BWa  
X
BWb  
X
L
H
H
H
H
H
X
L
L
L
H
L
Write All Bytes  
L
L
Write Byte a  
Write Byte b  
L
H
H
L
X
X
Read  
H
H
Key: X = don’t care, L = low, H = high, n = a, b; BWE  
,
BWn = internal write signal.  
Asynchronous Truth Table  
Operation  
Snooze mode  
ZZ  
H
L
OE  
X
I/O Status  
High-Z  
L
Dout  
Read  
L
H
High-Z  
Write  
L
X
Din, High-Z  
High-Z  
Deselected  
L
X
Notes:  
1. X means “Don’t Care”  
2. ZZ pin is pulled down internally  
3. For write cycles that follows read cycles, the output buffers must be disabled with OE, otherwise data bus contention will occur.  
4. Snooze mode means power down state of which stand-by current does not depend on cycle times  
5. Deselected means power down state of which stand-by current depends on cycle times  
Burst sequence table  
Interleaved burst address (LBO = 1)  
A1 A0 A1 A0 A1 A0 A1 A0  
Linear burst address (LBO = 0)  
A1 A0 A1 A0 A1 A0 A1 A0  
1st Address  
2nd Address  
3rd Address  
4th Address  
1st Address  
2nd Address  
3rd Address  
4th Address  
0 0  
0 1  
1 0  
1 1  
0 1  
0 0  
1 1  
1 0  
1 0  
1 1  
0 0  
0 1  
1 1  
1 0  
0 1  
0 0  
0 0  
0 1  
1 0  
1 1  
0 1  
1 0  
1 1  
1 0  
1 0  
1 1  
0 0  
0 1  
1 1  
0 0  
0 1  
1 0  
1/31/05; v.1.2  
Alliance Semiconductor  
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