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AS7C33256PFD18B-200TQIN 参数 Datasheet PDF下载

AS7C33256PFD18B-200TQIN图片预览
型号: AS7C33256PFD18B-200TQIN
PDF下载: 下载PDF文件 查看货源
内容描述: [Standard SRAM, 256KX18, 3ns, CMOS, PQFP100, 14 X 20 MM, LEAD FREE, TQFP-100]
分类和应用: 静态存储器内存集成电路
文件页数/大小: 19 页 / 536 K
品牌: ISSI [ INTEGRATED SILICON SOLUTION, INC ]
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AS7C33256PFD18B  
®
Signal descriptions  
Signal  
CLK  
I/O  
Properties  
CLOCK  
Description  
I
Clock. All inputs except OE, ZZ, LBO are synchronous to this clock.  
Address. Sampled when all chip enables are active and ADSC or ADSP are  
asserted.  
A,A0,A1  
DQ[a,b]  
I
SYNC  
I/O SYNC  
Data. Driven as output when the chip is enabled and OE is active.  
Master chip enable. Sampled on clock edges when ADSP or ADSC is active.  
When CE0 is inactive, ADSP is blocked. Refer to the Synchronous Truth Table for  
more information.  
CE0  
I
SYNC  
Synchronous chip enables. Active HIGH and active LOW, respectively. Sampled  
on clock edges when ADSC is active or when CE0 and ADSP are active.  
CE1, CE2  
ADSP  
I
I
SYNC  
SYNC  
Address strobe (processor). Asserted LOW to load a new address or to enter  
standby mode.  
Address strobe (controller). Asserted LOW to load a new address or to enter  
standby mode.  
ADSC  
ADV  
GWE  
I
I
I
SYNC  
SYNC  
SYNC  
Burst advance. Asserted LOW to continue burst read/write.  
Global write enable. Asserted LOW to write all 18 bits. When HIGH, BWE and  
BW[a,b] control write enable.  
Byte write enable. Asserted LOW with GWE = HIGH to enable effect of BW[a,b]  
inputs.  
BWE  
BW[a,b]  
OE  
I
I
I
I
SYNC  
Write enables. Used to control write of individual bytes when GWE = HIGH and  
BWE = LOW. If any of BW[a,b] is active with GWE = HIGH and BWE = LOW  
the cycle is a write cycle. If all BW[a,b] are inactive, the cycle is a read cycle.  
SYNC  
Asynchronous output enable. I/O pins are driven when OE is active and the chip is  
in read mode.  
ASYNC  
STATIC  
Selects Burst mode. When tied to V or left floating, device follows interleaved  
DD  
LBO  
Burst order. When driven Low, device follows linear Burst order. This signal is  
internally pulled High.  
Snooze. Places device in low power mode; data is retained. Connect to GND if  
unused.  
ZZ  
I
-
ASYNC  
-
NC  
No connect  
Snooze Mode  
SNOOZE MODE is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of  
SNOOZE MODE is dictated by the length of time the ZZ is in a High state.  
The ZZ pin is an asynchronous, active high input that causes the device to enter SNOOZE MODE.  
When the ZZ pin becomes a logic High, ISB2 is guaranteed after the time tZZI is met. After entering SNOOZE MODE, all inputs except ZZ  
is disabled and all outputs go to High-Z. Any operation pending when entering SNOOZE MODE is not guaranteed to successfully complete.  
Therefore, SNOOZE MODE (READ or WRITE) must not be initiated until valid pending operations are completed. Similarly, when exiting  
SNOOZE MODE during tPUS, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SNOOZE  
MODE.  
1/31/05; v.1.2  
Alliance Semiconductor  
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