欢迎访问ic37.com |
会员登录 免费注册
发布采购

AS7C331MPFS18A-225BI 参数 Datasheet PDF下载

AS7C331MPFS18A-225BI图片预览
型号: AS7C331MPFS18A-225BI
PDF下载: 下载PDF文件 查看货源
内容描述: [Standard SRAM, 1MX18, 6.9ns, CMOS, PBGA165, BGA-165]
分类和应用: 静态存储器内存集成电路
文件页数/大小: 21 页 / 411 K
品牌: ISSI [ INTEGRATED SILICON SOLUTION, INC ]
 浏览型号AS7C331MPFS18A-225BI的Datasheet PDF文件第9页浏览型号AS7C331MPFS18A-225BI的Datasheet PDF文件第10页浏览型号AS7C331MPFS18A-225BI的Datasheet PDF文件第11页浏览型号AS7C331MPFS18A-225BI的Datasheet PDF文件第12页浏览型号AS7C331MPFS18A-225BI的Datasheet PDF文件第14页浏览型号AS7C331MPFS18A-225BI的Datasheet PDF文件第15页浏览型号AS7C331MPFS18A-225BI的Datasheet PDF文件第16页浏览型号AS7C331MPFS18A-225BI的Datasheet PDF文件第17页  
AS7C331MPFS18A  
®
TAP AC test conditions  
Input pulse levels. . . . . . . . . . . . . . . Vss to 2.5V  
TAP AC output load equivalent  
ꢎ,ꢏ28  
Input rise and fall times. . . . . . . . . . . . . . . 1 ns  
Input timing reference levels. . . . . . . . . . 1.25V  
Output reference levels . . . . . . . . . . . . . . 1.25V  
Test load termination supply voltage. . . . 1.25V  
2ꢕΩ  
ꢄꢂꢓ  
ꢏꢕ"ꢌ  
=12ꢕΩ  
3.3V V , TAP DC electrical characteristics and operating conditions  
DD  
o
o
(+10 C < T < +110 C and +3.135V < V < +3.465V unless otherwise noted)  
J
DD  
Description  
Conditions  
Symbol  
Min  
2.0  
Max  
VDD + 0.3  
0.8  
Units  
V
Notes  
1, 2  
Input high (logic 1) voltage  
Input low (logic 0) voltage  
Input leakage current  
V
IH  
V
IL  
-0.3  
-5.0  
V
1, 2  
0V V VDD  
IL  
5.0  
µA  
IN  
I
Outputs disabled,  
Output leakage current  
ILO  
-5.0  
5.0  
µA  
0V V VDDQ(DQx)  
IN  
Output low voltage  
Output low voltage  
Output high voltage  
Output high voltage  
IOLC = 100µA  
V
0.7  
0.8  
V
V
V
V
1
1
1
1
OL1  
I
OLT = 2mA  
IOHS = -100µA  
OHT = -2mA  
V
OL2  
V
OH1  
2.9  
2.0  
I
V
OH2  
2.5V V , TAP DC electrical characteristics and operating conditions  
DD  
o
o
(+10 C < T < +110 C and +2.4V < V < +2.6V unless otherwise noted)  
J
DD  
Description  
Conditions  
Symbol  
Min  
1.7  
Max  
VDD + 0.3  
0.7  
Units  
V
Notes  
1, 2  
Input high (logic 1) voltage  
Input low (logic 0) voltage  
Input leakage current  
V
IH  
V
IL  
-0.3  
-5.0  
V
1, 2  
0V V VDD  
IL  
I
5.0  
µA  
IN  
Outputs disabled,  
Output leakage current  
ILO  
-5.0  
5.0  
µA  
0V V VDDQ(DQx)  
IN  
Output low voltage  
Output low voltage  
Output high voltage  
Output high voltage  
IOLC = 100µA  
V
0.2  
0.7  
V
V
V
V
1
1
1
1
OL1  
I
OLT = 2mA  
OHS = -100µA  
IOHT = -2mA  
V
OL2  
I
V
2.1  
1.7  
OH1  
V
OH2  
1. All voltage referenced to V (GND).  
SS  
2. Overshoot: V (AC) V + 1.5V for t tKHKH/ 2  
IH  
DD  
Undershoot: V (AC) -0.5 for t tKHKH/ 2  
IL  
Power-up: V +2.6V and VDD 2.4V and VDDQ 1.4V for t 200ms  
IH  
During normal operation, V  
must not exceed V . Control input signals (such as LD, R/ W, etc.) may not have pulsed widths less than t  
(Min) or oper-  
KHKL  
DDQ  
DD  
ate at frequencies exceeding f (Max).  
KF  
12/ 2/ 02, v. 0.9.2 Advance Info  
Alliance Semiconductor  
13 of 21