AS7C331MPFS18A
®
Reserved
Do not use a reserved instruction.These instructions are not implemented but are reserved for future use.
TAP timing diagram
ꢎ
ꢏ
.
7
2
6
ꢄꢘ!ꢝꢖꢉ$ꢙ 9
:ꢄꢉ+;
ꢝ
ꢝ
ꢝ
ꢄꢋꢄꢋ
ꢄꢋꢄꢐ
ꢄꢐꢄꢋ
ꢄꢘ!ꢝꢖ'ꢙ*ꢘꢖꢊꢘ$ꢘ ꢝ
:ꢄ'ꢊ;
ꢝ ꢝ
'8ꢄꢋ ꢄꢋ'ꢍ
ꢄꢘ!ꢝꢖꢂꢞꢝꢞꢆꢇꢛ
:ꢄꢂꢇ;
ꢝ
ꢄꢐꢓ8
ꢝ
ꢝ
ꢂ8ꢄꢋ
ꢄꢋꢂꢍ
ꢝ
ꢄꢐꢓꢍ
ꢄꢘ!ꢝꢖꢂꢞꢝꢞꢆꢓ%ꢝ
:ꢄꢂꢓ;
ꢀꢛ*ꢘ&(ꢛꢘ*
ꢂꢙꢛRꢝꢖ ꢞꢚꢘ
TAP AC electrical characteristics
o
o
For notes 1 and 2, +10 C < T < +110 C and +2.4V < V < +2.6V.
J
DD
Description
Symbol
Min Max Units
Clock
Clock cycle time
Clock frequency
Clock high time
Clock low time
Output Times
tTHTH
fTF
tTHTL
tTLTH
100
ns
10 MHz
ns
40
40
ns
TCK low to TDO unknown
TCK low to TDO valid
TDI valid to TCK high
TCK high to TDI invalid
Setup Times
tTLOX
tTLOV
tDVTH
tTHDX
0
ns
20
ns
ns
ns
10
10
TMS setup
tMVTH
1
tCS
10
10
ns
ns
Capture setup
Hold Times
TMS hold
tTHMX
tCH1
10
10
ns
ns
Capture hold
t
t
1 CS and CH refer to the setup and hold time requirements of latching data
from the boundary scan register.
2
Test conditions are specified using the load in the figure TAP AC output
load equivalent.
12/ 2/ 02, v. 0.9.2 Advance Info
Alliance Semiconductor
12 of 21
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
