AS7C331MFT18A
®
Functional description
The AS7C331MFT18A is a high-performance CMOS 16-Mbit synchronous Static Random Access Memory (SRAM) device
organized as 1,048,576 words x18 bits.
Fast cycle times of 7.5/8.5/10/12 ns with clock access times (t
CD
) of 6.8/7.5/8.5/10 ns. Three chip enable (CE) inputs permit
easy memory expansion. Burst operation is initiated in one of two ways: the controller address strobe (ADSC), or the
processor address strobe (ADSP). The burst advance pin (ADV) allows subsequent internally generated burst addresses.
Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip
address register when ADSP is sampled LOW, the chip enables are sampled active, and the output buffer is enabled with OE.
In a read operation, the data accessed by the current address registered in the address registers by the positive edge of CLK is
carried to the data-out buffers. ADV is ignored on the clock edge that samples ADSP asserted, but it is sampled on all
subsequent clock edges. Address is incremented internally for the next access of the burst when ADV is sampled LOW and
both address strobes are HIGH. Burst mode is selectable with the LBO input. With LBO unconnected or driven HIGH, burst
operations use an interleaved count sequence. With LBO driven LOW, the device uses a linear count sequence.
Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable
GWE writes all 18 bits regardless of the state of individual BW[a,b] inputs. Alternately, when GWE is HIGH, one or more
bytes may be written by asserting BWE and the appropriate individual byte BWn signals.
BWn is ignored on the clock edge that samples ADSP LOW, but it is sampled on all subsequent clock edges. Output buffers
are disabled when BWn is sampled LOW, regardless of OE. Data is clocked into the data input register when BWn is sampled
LOW. Address is incremented internally to the next burst address if BWn and ADV are sampled LOW.
Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC
and ADSP are as follows:
ADSP must be sampled HIGH when ADSC is sampled LOW to initiate a cycle with ADSC.
WE signals are sampled on the clock edge that samples ADSC LOW (and ADSP HIGH).
Master chip enable CE0 blocks ADSP, but not ADSC.
The AS7C331MFT18A family operates from a core 3.3V power supply. I/Os use a separate power supply that can operate at
2.5V or 3.3V. These devices are available in 100-pin TQFP package.
TQFP capacitance
Parameter
Input capacitance
I/O capacitance
*Guaranteed not tested
Symbol
C
IN*
C
I/O*
Test conditions
V
IN
= 0V
V
OUT
= 0V
Min
-
-
Max
5
7
Unit
pF
pF
TQFP thermal resistance
Description
Thermal resistance
(junction to ambient)
1
Thermal resistance
(junction to top of case)
1
1 This parameter is sampled
Conditions
1–layer
Test conditions follow standard test methods and
procedures for measuring thermal impedance,
per EIA/JESD51
4–layer
Symbol
θ
JA
θ
JA
θ
JC
Typical
40
22
8
Units
°C/W
°C/W
°C/W
1/21/05, v 1.4
Alliance Semiconductor
4 of 19
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
