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AS7C252MFT18A-10TQIN 参数 Datasheet PDF下载

AS7C252MFT18A-10TQIN图片预览
型号: AS7C252MFT18A-10TQIN
PDF下载: 下载PDF文件 查看货源
内容描述: [Standard SRAM, 2MX18, 10ns, CMOS, PQFP100, 14 X 20 MM, LEAD FREE, TQFP-100]
分类和应用: 静态存储器内存集成电路
文件页数/大小: 19 页 / 508 K
品牌: ISSI [ INTEGRATED SILICON SOLUTION, INC ]
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AS7C252MFT18A  
®
Functional description  
The AS7C252MFT18A is a high-performance CMOS 32-Mbit synchronous Static Random Access Memory (SRAM) device organized as  
2,097152 words × 18 bits.  
Fast cycle times of 8.5/10/12 ns with clock access times (tCD) of 7.5/8.5/10 ns. Three chip enable (CE) inputs permit easy memory expansion.  
Burst operation is initiated in one of two ways: the controller address strobe (ADSC), or the processor address strobe (ADSP). The burst  
advance pin (ADV) allows subsequent internally generated burst addresses.  
Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip address register  
when ADSP is sampled low, the chip enables are sampled active, and the output buffer is enabled with OE. In a read operation, the data  
accessed by the current address registered in the address registers by the positive edge of CLK are carried to the data-out buffer. ADV is  
ignored on the clock edge that samples ADSP asserted, but is sampled on all subsequent clock edges. Address is incremented internally for  
the next access of the burst when ADV is sampled low and both address strobes are high. Burst mode is selectable with the LBO input. With  
LBO unconnected or driven high, burst operations use an interleaved count sequence. With LBO driven low, the device uses a linear count  
sequence.  
Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable GWE writes all 18  
bits regardless of the state of individual BW[a,b] inputs. Alternately, when GWE is high, one or more bytes may be written by asserting BWE  
and the appropriate individual byte BWn signals.  
BWn is ignored on the clock edge that samples ADSP low, but it is sampled on all subsequent clock edges. Output buffers are disabled when  
BWn is sampled LOW regardless of OE. Data is clocked into the data input register when BWn is sampled low. Address is incremented  
internally to the next burst address if BWn and ADV are sampled low.  
Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC and ADSP are  
as follows:  
• ADSP must be sampled high when ADSC is sampled low to initiate a cycle with ADSC.  
• WE signals are sampled on the clock edge that samples ADSC low (and ADSP high).  
• Master chip enable CE0 blocks ADSP, but not ADSC.  
The AS7C252MFT18A family operates from a core 2.5V power supply. These devices are available in 100-pin TQFP package.  
TQFP capacitance  
Parameter  
Input capacitance  
Symbol  
Test conditions  
VIN = 0V  
Min  
Max  
Unit  
pF  
*
CIN  
-
-
5
7
*
I/O capacitance  
CI/O  
VOUT = 0V  
pF  
*Guaranteed not tested  
TQFP thermal resistance  
Description  
Conditions  
Symbol  
Typical  
40  
Units  
°C/W  
°C/W  
1–layer  
4–layer  
θJA  
θJA  
Thermal resistance  
(junction to ambient)1  
Test conditions follow standard test methods and  
procedures for measuring thermal impedance,  
per EIA/JESD51  
22  
Thermal resistance  
θJC  
8
°C/W  
(junction to top of case)1  
1 This parameter is sampled  
1/17/05, v 1.2  
Alliance Semiconductor  
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