75V16F64GS16
ISSI
C
D
E
F
G
H
J
K
®
PIN CONFIGURATION (64 Mb Flash and 16 Mb PSRAM)
PACKAGE CODE: D 65 BALL FBGA (Top View) (9.00 mm x 9.00 mm Body, 0.8 mm Ball Pitch)
A
B
10
NC
NC
9
NC
A15
A21
NC
A16
Vccf
GND
NC
8
A11
A12
A13
A14
NC
DQ15
DQ7
DQ14
7
A8
A19
A9
A10
DQ6
DQ13
DQ12
DQ5
6
WE
CE2r
A20
DQ4
Vccr
NC
5
WP/ACC RESET
RY/BY
DQ3
Vccf
DQ11
4
LB
UB
A18
A17
DQ1
DQ9
OE
CEf
DQ10
DQ2
3
A7
A6
A5
A4
GND
DQ0
CE1r
DQ8
Common
Flash Only
NC
A3
A2
A1
A0
NC
2
1
NC
NC
NC
PSRAM Only
PIN DESCRIPTIONS
A0-A19
A20-A21
RESET
RY/BY
CEf
OE
WE
Address Inputs, Common
Address Inputs, Flash
LB
UB
WP/ACC
RY/BY
NC
Vccf
GND
Vccr
Lower-byte Control, PSRAM
Upper-byte Control, PSRAM
DQ0-DQ15 Data Inputs/Outputs, Common
Hardware Reset Pin/Acceleration, Flash
Write Protect/Acceleration, Flash
Ready/Busy Output
No Internal Connection
Device Power Supply, Flash
Device Ground, Common
Device Power, PSRAM
CE1r,CE2r
Chip Enable, PSRAM
Ready/Busy Output, Flash Open Drain Output
Chip Enable, Flash
Output Enable, Common
Write Enable, Common
2
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
08/01/02
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
