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66WVE4M16ALL-70TLI 参数 Datasheet PDF下载

66WVE4M16ALL-70TLI图片预览
型号: 66WVE4M16ALL-70TLI
PDF下载: 下载PDF文件 查看货源
内容描述: [Pseudo Static RAM, 4MX16, 70ns, CMOS, PDSO48, TSOP1-48]
分类和应用: 光电二极管内存集成电路
文件页数/大小: 30 页 / 676 K
品牌: ISSI [ INTEGRATED SILICON SOLUTION, INC ]
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IS66WVE4M16ALL
Advanced Information
Functional Description
All functions for the device are listed below in Table 2.
Table 2. Functional Descriptions
Mode
Standby
Read
Write
No operation
PAR
DPD
Load
Configuration
register
Power
Standby
Active
Active
Idle
PAR
DPD
Active
CE#
H
L
L
L
H
H
L
WE#
X
H
L
X
X
X
L
OE#
X
L
X
X
X
X
X
UB#/LB#
X
L
L
X
X
X
X
ZZ#
H
H
H
H
L
L
L
DQ
[15:0]
4
High-Z
Data-Out
Data-In
X
High-Z
High-Z
High-Z
Note
2,5
1,4
1,3,4
4,5
6
6
Notes
1. When UB# and LB# are in select mode (LOW), DQ0~DQ15 are affected as shown.
When only LB# is in select mode, DQ0~DQ7 are affected as shown. When only UB# is
in select mode, DQ8~DQ15 are affected as shown.
2. When the device is in standby mode, control inputs (WE#, OE#), address inputs, and data
inputs/outputs are internally isolated from any external influence.
3. When WE# is active, the OE# input is internally disabled and has no effect on the I/Os.
4. The device will consume active power in this mode whenever addresses are changed.
5. Vin=VDDQ or 0V, all device pins be static (unswitched) in order to achieve standby current.
6. DPD is enabled when configuration register bit CR[4] is “0”; otherwise, PAR is enabled.
Rev.00C | March 2010
www.issi.com
- SRAM@issi.com
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