IS66WVC2M16ALL
Advanced Information
General Description
CellularRAM™ (Trademark of MicronTechnology Inc.) products are high-speed, CMOS
pseudo-static random access memory developed for low-power, portable applications.
The 32Mb DRAM core device is organized as 2 Meg x 16 bits. This device is a variation of
the industry-standard Flash control interface that dramatically increase READ/WRITE
bandwidth compared with other low-power SRAM or Pseudo SRAM offerings.
To operate seamlessly on a burst Flash bus, CellularRAM products have incorporated a
transparent self-refresh mechanism. The hidden refresh requires no additional support
from the system memory controller and has no significant impact on device read/write
performance.
Two user-accessible control registers define device operation. The bus configuration
register (BCR) defines how the CellularRAM device interacts with the system memory
bus and is nearly identical to its counterpart on burst mode Flash devices.
The refresh configuration register (RCR) is used to control how refresh is performed on
the DRAM array. These registers are automatically loaded with default settings during
power-up and can be updated anytime during normal operation.
Special attention has been focused on standby current consumption during self refresh.
CellularRAM products include three mechanisms to minimize standby current. Partial
array refresh (PAR) enables the system to limit refresh to only that part of the DRAM
array that contains essential data. Temperature-compensated refresh (TCR) uses an
on-chip sensor to adjust the refresh rate to match the device temperature — the refresh
rate decreases at lower temperatures to minimize current consumption during standby.
Deep power-down (DPD) enables the system to halt the refresh operation altogether
when no vital information is stored in the device. The system-configurable refresh
mechanisms are adjusted through the RCR.
This CellularRAM device is compliant with the industry-standard CellularRAM 1.5
feature set established by the CellularRAM Workgroup. It includes support for both
variable and fixed latency, with three drive strengths, a variety of wrap options, and a
device ID register (DIDR).
A0~A20
Address
Decode Logic
Input
/Output
Mux
2048K X 16
DRAM
Memory Array
Refresh
Configuration Register
(RCR)
And
Buffers
Device ID Register
(DIDR)
Bus
Configuration Register
(BCR)
CE#
WE#
OE#
CLK
Control
Logic
ADV#
CRE
LB#
UB#
WAIT
DQ0~DQ15
[ Functional Block Diagram]
2
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Rev.00B | March 2010
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
