IS62C1024L
AC WAVEFORMS
WRITE CYCLE NO. 1 (WE Controlled)
(1,2)
WE
t
WC
ISSI
®
ADDRESS
t
SCE1
t
HA
CE1
t
SCE2
CE2
t
AW
t
PWE
(4)
t
SA
t
HZWE
HIGH-Z
WE
t
LZWE
DOUT
DATA UNDEFINED
t
SD
t
HD
DIN
DATA-IN VALID
WRITE CYCLE NO. 2 (CE1 CE2 Controlled)
(1,2)
CE1,
CE1
t
WC
ADDRESS
t
SA
t
SCE1
t
HA
CE1
t
SCE2
CE2
t
AW
t
PWE
(4)
WE
t
HZWE
t
LZWE
HIGH-Z
DOUT
DATA UNDEFINED
t
SD
t
HD
DIN
DATA-IN VALID
Notes:
1. The internal write time is defined by the overlap of
CE1
LOW, CE2 HIGH and
WE
LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if
OE
= V
IH
.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. E
11/26/03
7
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
