®
ISSI
IS41LV16100B
ELECTRICAL CHARACTERISTICS(1)
(Recommended Operating Conditions unless otherwise noted.)
Symbol
Parameter
Test Condition
Speed Min. Max.
Unit
IIL
InputLeakageCurrent
Any input 0V ≤ VIN ≤ VDD
–10
10
µA
Other inputs not under test = 0V
IIO
OutputLeakageCurrent
Output is disabled (Hi-Z)
–10
10
µA
0V ≤ VOUT ≤ VDD
VOH
VOL
ICC1
Output High Voltage Level
Output Low Voltage Level
StandbyCurrent:TTL
IOH = –2.0 mA (3.3V)
IOL = 2.0 mA (3.3V)
2.4
—
—
V
V
0.4
RAS, LCAS, UCAS ≥ VIH Commercial 3.3V
—
—
3
4
mA
mA
Industrial 3.3V
ICC2
ICC3
StandbyCurrent:CMOS
RAS, LCAS, UCAS ≥ VDD – 0.2V
3.3V
—
2
mA
mA
OperatingCurrent:
RAS, LCAS, UCAS,
Address Cycling, tRC = tRC (min.)
-50
-60
—
—
180
170
RandomRead/Write(2,3,4)
AveragePowerSupplyCurrent
ICC4
ICC5
OperatingCurrent:
RAS = VIL, LCAS, UCAS,
Cycling tPC = tPC (min.)
-50
-60
—
—
180
170
mA
mA
mA
EDOPageMode(2,3,4)
AveragePowerSupplyCurrent
RefreshCurrent:
RAS Cycling, LCAS, UCAS ≥ VIH
tRC = tRC (min.)
-50
-60
—
—
180
170
RAS-Only(2,3)
AveragePowerSupplyCurrent
ICC6
RefreshCurrent:
CBR(2,3,5)
RAS, LCAS, UCAS Cycling
tRC = tRC (min.)
-50
-60
—
—
180
170
AveragePowerSupplyCurrent
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each EDO page cycle.
5. Enables on-chip refresh and address counters.
6
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
04/13/05
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
