®
ISSI
IS41LV16100B
Functional Description
Auto Refresh Cycle
The IS41LV16100B is a CMOS DRAM optimized for high-
speed bandwidth, low power applications. During READ or
WRITE cycles, each bit is uniquely addressed through the
16addressbits.Theseareenteredtenbits(A0-A9)at time.
The row address is latched by the Row Address Strobe
(RAS). The column address is latched by the Column
Address Strobe (CAS). RAS is used to latch the first nine bits
and CAS is used to latch the latter nine bits.
To retain data, 1,024 refresh cycles are required in each
16 ms period. There are two ways to refresh the memory.
1. Byclockingeachofthe1,024rowaddresses(A0throughA9)
with RAS at least once every 128 ms. Any read, write, read-
modify-writeorRAS-onlycyclerefreshestheaddressedrow.
2. Using a CAS-before-RAS refresh cycle. CAS-before-
RAS refresh is activated by the falling edge of RAS,
while holding CAS LOW. In CAS-before-RAS refresh
cycle, an internal 9-bit counter provides the row ad-
dresses and the external address inputs are ignored.
TheIS41LV16100BhastwoCAScontrols, LCAS andUCAS.
The LCAS and UCAS inputs internally generates a CAS signal
functioning in an identical manner to the single CAS input on
theother1Mx16DRAMs.ThekeydifferenceisthateachCAS
controlsitscorrespondingI/Otristatelogic(inconjunctionwith
OE and WE and RAS). LCAS controls I/O0 through I/O7 and
UCAS controls I/O8 through I/O15.
CAS-before-RAS is a refresh-only mode and no data
access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.
Extended Data Out Page Mode
TheIS41LV16100B CASfunctionisdeterminedbythefirst
CAS (LCAS or UCAS) transitioning LOW and the last
transitioning back HIGH. The two CAS controls give the
IS41LV16100BbothBYTEREADandBYTEWRITE cycle
capabilities.
EDOpagemodeoperationpermitsall1,024columnswithin
a selected row to be randomly accessed at a high data rate.
In EDO page mode read cycle, the data-out is held to the
next CAS cycle’s falling edge, instead of the rising edge.
For this reason, the valid data output time in EDO page
mode is extended compared with the fast page mode. In
the fast page mode, the valid data output time becomes
shorter as the CAS cycle time becomes shorter. There-
fore, in EDO page mode, the timing margin in read cycle
is larger than that of the fast page mode even if the CAS
cycle time becomes shorter.
Memory Cycle
A memory cycle is initiated by bring RAS LOW and it is
terminated by returning both RAS and CAS HIGH. To
ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or
aborted before the minimum tRAS time has expired. A new
cycle must not be initiated until the minimum precharge
time tRP, tCP has elapsed.
In EDO page mode, due to the extended data function, the
CAS cycle time can be shorter than in the fast page mode
if the timing margin is the same.
Read Cycle
The EDO page mode allows both read and write opera-
tions during one RAS cycle, but the performance is
equivalent to that of the fast page mode in that case.
A read cycle is initiated by the falling edge of CAS or OE,
whichever occurs last, while holding WE HIGH. The column
address must be held for a minimum time specified by tAR.
Data Out becomes valid only when tRAC, tAA, tCAC and tOEA
are all satisfied. As a result, the access time is dependent
on the timing relationships between these parameters.
Power-On
After application of the VDD supply, an initial pause of
200 µs is required followed by a minimum of eight
initialization cycles (any combination of cycles contain-
ing a RAS signal).
Write Cycle
A write cycle is initiated by the falling edge of CAS and WE,
whichever occurs last. The input data must be valid at or
before the falling edge of CAS or WE, whichever occurs first.
During power-on, it is recommended that RAS track with
VDD or be held at a valid VIH to avoid current surges.
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Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
04/13/05
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
