IS61NLP12832B
IS61NLP12836B/IS61NVP12836B
IS61NLP25618A/IS61NVP25618A
PIN CONFIGURATION
100-Pin TQFP
NC
BWb
BWa
CKE
ADV
NC
CE2
CE2
V
DD
Vss
CLK
WE
OE
NC
NC
CE
A
A
NC
NC
NC
V
DDQ
Vss
NC
NC
DQb
DQb
Vss
V
DDQ
DQb
DQb
NC
V
DD
NC
Vss
DQb
DQb
V
DDQ
Vss
DQb
DQb
DQPb
NC
Vss
V
DDQ
NC
NC
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
10
71
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
V
DD
NC
NC
A
A
A
A
A
MODE
A
A
A
A
A1
A0
NC
NC
Vss
A
A
A
A
A
NC
NC
V
DDQ
Vss
NC
DQPa
DQa
DQa
Vss
V
DDQ
DQa
DQa
Vss
NC
V
DD
ZZ
DQa
DQa
V
DDQ
Vss
DQa
DQa
NC
NC
Vss
V
DDQ
NC
NC
NC
256K x 18
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
Synchronous Address Inputs
Synchronous Clock
Synchronous Burst Address Advance
Synchronous Byte Write Enable
Write Enable
Clock Enable
Ground for Core
Not Connected
CE,
CE2,
CE2
OE
DQa-DQd
DQPa-DQPd
MODE
V
dd
V
SS
V
ddq
ZZ
Synchronous Chip Enable
Output Enable
Synchronous Data Input/Output
Parity Data I/O
Burst Sequence Selection
+3.3V/2.5V Power Supply
Ground for output Buffer
Isolated Output Buffer Supply: +3.3V/2.5V
Snooze Enable
A
CLK
ADV
BWa-BWd
WE
CKE
Vss
NC
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
09/10/07
9
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
