IS61NLP12832B
IS61NLP12836B/IS61NVP12836B
IS61NLP25618A/IS61NVP25618A
119-PIN
PBgA PACKAgE
CONFIGURATION
1
2
3
256K x 18 (TOP VIEW)
4
5
6
7
A
B
C
D
E
F
V
DDQ
NC
NC
DQb
NC
V
DDQ
NC
DQb
V
DDQ
NC
DQb
V
DDQ
DQb
NC
NC
NC
V
DDQ
A
CE2
A
NC
DQb
NC
DQb
NC
V
DD
DQb
NC
DQb
NC
DQPb
A
A
NC
A
A
A
V
SS
V
SS
V
SS
BWb
V
SS
NC
V
SS
NC
V
SS
V
SS
V
SS
MODE
A
NC
NC
ADV
V
DD
NC
CE
OE
NC
WE
V
DD
CLK
NC
CKE
A
1
*
A
0
*
V
DD
NC
NC
A
A
A
Vss
Vss
Vss
NC
Vss
NC
Vss
BWa
Vss
Vss
Vss
NC
A
NC
A
CE2
A
DQPa
NC
DQa
NC
DQa
V
DD
NC
DQa
NC
DQa
NC
A
A
NC
V
DDQ
NC
NC
NC
DQa
V
DDQ
DQa
NC
V
DDQ
DQa
NC
V
DDQ
NC
DQa
NC
ZZ
V
DDQ
G
H
J
K
L
M
N
P
R
T
U
Note:
A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
A
A0, A1
ADV
WE
CLK
CKE
CE
CE2
CE2
BWx (x=a,b)
Pin Name
Address Inputs
Synchronous Burst Address Inputs
Synchronous Burst Address Advance/
Load
Synchronous Read/Write Control
Input
Synchronous Clock
Clock Enable
Synchronous Chip Select
Synchronous Chip Select
Synchronous Chip Select
Synchronous Byte Write Inputs
OE
ZZ
MODE
V
dd
V
SS
NC
DQa-DQb
DQPa-Pb
V
ddq
Output Enable
Power Sleep Mode
Burst Sequence Selection
Power Supply
Ground
No Connect
Data Inputs/Outputs
Parity Data I/O
Output Power Supply
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
09/10/07
7
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
