IRLR/U120NPbF
800
C, Capacitance (pF)
600
C
iss
V
GS
, Gate-to-Source Voltage (V)
V
GS
= 0V,
f = 1MHz
C
iss
= C
gs
+ C
gd
, C
ds
SHORTED
C
rss
= C
gd
C
oss
= C
ds
+ C
gd
15
I
D
= 6.0A
V
DS
= 80V
V
DS
= 50V
V
DS
= 20V
12
9
400
C
oss
200
6
C
rss
3
0
1
10
100
A
0
0
5
10
FOR TEST CIRCUIT
SEE FIGURE 13
15
20
25
A
V
DS
, Drain-to-Source Voltage (V)
Q
G
, Total Gate Charge (nC)
Fig 5.
Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 6.
Typical Gate Charge Vs.
Gate-to-Source Voltage
100
100
I
SD
, Reverse Drain Current (A)
OPERATION IN THIS AREA LIMITED
BY R
DS(on)
10µs
10
T
J
= 175°C
T
J
= 25°C
I
D
, Drain Current (A)
10
100µs
1ms
1
10ms
1
0.1
0.4
0.6
0.8
1.0
V
GS
= 0V
1.2
A
0.1
1
T
C
= 25°C
T
J
= 175°C
Single Pulse
10
100
1.4
1000
A
V
SD
, Source-to-Drain Voltage (V)
V
DS
, Drain-to-Source Voltage (V)
Fig 7.
Typical Source-Drain Diode
Forward Voltage
Fig 8.
Maximum Safe Operating Area
4
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