(
)
IR2136(2)(3)(5)(6)(7)(8)
J&S)&(PbF
Dynamic Electrical Characteristics
V
= V = V
= 15V, V
= V = COM, TA = 25oC and C = 1000 pF unless otherwise specified.
L
S1,2,3 SS
CC
BS
BIAS
Symbol
Definition
Min. Typ. Max. Units Test Conditions
t
Turn-on propagation delay
IR2136(2)(3)(5)(8)
IR21366(7)
300
425
250
400
180
125
50
550
on
—
—
V
IN
= 0 & 5V
t
Turn-off propagation delay
IR2136(2)(3)(5)(8)
IR21366(7)
250
—
550
—
off
t
Turn-on rise time
—
190
75
r
t
Turn-off fall time
—
f
t
ENABLE low to output
shutdown propagation delay
IR2136(2)(3)(5)(8)
IR21366(7)
300
100
500
100
450
250
750
150
600
400
1000
—
V
V
= 0V or 5V
EN
IN, EN
nS
t
t
ITRIP to output shutdown propagation delay
ITRIP blanking time
V
ITRIP
= 5V
ITRIP
t
bl
V
= 0V or 5V
IN
V
ITRIP
= 5V
t
ITRIP to FAULT propagation delay
400
100
1.3
600
200
1.65
800
—
2
V
= 0V or 5V
FLT
IN
V
ITRIP
= 5V
Input filter time (HIN, LIN, EN)
(IR2136(2)(3)(5)(8) only)
V
= 0 & 5V
IN
FILIN
t
FAULT clear time RCIN: R=2meg, C=1nF
mS
nS
V
= 0V or 5V
FLTCLR
IN
V
ITRIP
= 0V
DT
MT
Deadtime
220
—
290
40
360
75
V
= 0 & 5V
IN
Matching delay ON and OFF
External dead
time
MDT
Matching delay, max (t ,t ) - min (t ,t ),
on off on off
—
25
70
(ton,toff are applicable to all 3 channels)
>400nsec
PM
Output pulse width matching, PWin -PWout (fig.2)
—
40
75
NOTE: For high side PWM, HIN pulse width must be ≥ 1µsec
VCC
<UVCC
15V
VBS
X
ITRIP
X
ENABLE
FAULT
LO1,2,3
HO1,2,3
X
0 (note 1)
high imp
high imp
0 (note 2)
high imp
0
LIN1,2,3
LIN1,2,3
0
0
<UVBS
15V
0V
5V
5V
5V
0V
0
15V
0V
HIN1,2,3
15V
15V
>V
0
0
ITRIP
15V
15V
0V
0
Note: A shoot-through prevention logic prevents LO1,2,3 and HO1,2,3 for each channel from turning on simultaneously.
Note 1: UVCC is not latched, when VCC>UVCC, FAULT returns to high impedance.
Note 2: When ITRIP <V , FAULT returns to high-impedance after RCIN pin becomes greater than 8V (@ VCC = 15V)
ITRIP
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5
INFINEON [ Infineon ]
