X9258
A.C. TEST CONDITIONS
Test Circuit #3 SPICE Macro Model
Input pulse levels
V
x 0.1 to V
x 0.5
x 0.9
CC
CC
10ns
Macro Model
Input rise and fall times
Input and output timing level
R
TOTAL
V
CC
R
R
L
H
C
L
C
H
C
EQUIVALENT A.C. LOAD CIRCUIT
W
10pF
5V
2.7V
10pF
25pF
1533Ω
R
W
SDA Output
100pF
100pF
AC TIMING (Over recommended operating condition)
Symbol Parameter
Min.
Max.
Unit
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
f
Clock frequency
400
SCL
t
Clock cycle time
2500
600
1300
600
600
600
100
30
CYC
t
Clock high time
HIGH
t
Clock low time
LOW
t
Start setup time
SU:STA
HD:STA
SU:STO
t
Start hold time
t
Stop setup time
t
SDA data input setup time
SDA data input hold time
SCL and SDA rise time
SCL and SDA fall time
SU:DAT
HD:DAT
t
t
300
300
900
R
t
F
t
SCL low to SDA data output valid time
SDA data output hold time
AA
t
50
50
DH
T
Noise suppression time constant at SCL and SDA inputs
Bus free rime (prior to any transmission)
WP, A0, A1, A2 and A3 setup time
I
t
1300
0
BUF
t
SU:WPA
t
WP, A0, A1, A2 and A3 hold time
0
HD:WPA
HIGH-VOLTAGE WRITE CYCLE TIMING
Symbol
Parameter
Typ.
Max.
Unit
t
High-voltage write cycle time (store instructions)
5
10
ms
WR
FN8168.1
13
May 6, 2005
INTERSIL [ Intersil ]
