X9258
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Typ.
Max.
Unit
Test Conditions
I
V
supply current (Nonvol-
1
mA
f = 400kHz, SDA = Open,
SCL
Other Inputs = V
SS
CC1
CC
atile Write)
I
V
supply current (move
100
µA
f
= 400kHz, SDA = Open,
CC2
CC
wiper, write, read)
SCL
Other Inputs = V
SS
SCL = SDA = V , Addr. = V
SS
I
V
current (standby)
5
µA
µA
µA
V
SB
CC
CC
I
Input leakage current
Output leakage current
Input HIGH voltage
Input LOW voltage
Output LOW voltage
10
10
V
V
= V to V
SS CC
LI
IN
I
= V to V
SS CC
LO
OUT
V
V
x 0.7
V
+ 0.1
CC
IH
CC
-0.5
V
V
x 0.3
V
IL
CC
0.4
V
V
I
= 3mA
OL
OL
Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiom-
eter. It is a measure of the error in step size.
(3) MI = RTOT/255 or (V /R —V /R )/255, single pot
H
H
L
L
(4) Max. = all four arrays cascaded together, Typical = individual array resolutions.
ENDURANCE AND DATA RETENTION
Parameter
Minimum endurance
Data retention
Min.
100,000
100
Unit
Data changes per bit per register
years
CAPACITANCE
Symbol
Test
Max.
Unit
pF
Test Conditions
(5)
C
Input/output capacitance (SDA)
8
6
V
= 0V
= 0V
I/O
I/O
(5)
C
Input capacitance (A0, A1, A2, A3, and SCL)
pF
V
IN
IN
POWER-UP TIMING
Symbol
Parameter
Min.
Max.
1
Unit
(6)
t
Power-up to initiation of read operation
Power-up to initiation of write operation
ms
ms
PUR
(6)
t
5
PUW
(7)
t
V
V
Power up ramp
CC
0.2
50
V/msec
R
CC
POWER UP AND DOWN REQUIREMENT
The are no restrictions on the sequencing of the bias supplies V , V+, and V- provided that all three supplies reach
CC
their final values within 1msec of each other. At all times, the voltages on the potentiometer pins must be less than V+
and more than V-. The recall of the wiper position from nonvolatile memory is not in effect until all supplies reach their
final value. The V
ramp rate spec is always in effect.
CC
Notes: (5) This parameter is periodically sampled and not 100% tested.
(6) t and t are the delays required from the time the third (last) power supply (V , V+ or V-) is stable until the specific
PUR
PUW CC
instruction can be issued. These parameters are periodically sampled and not 100% tested.
(7) Sample tested only.
FN8168.1
12
May 6, 2005
INTERSIL [ Intersil ]
