ISL6562
Electrical Specifications
PARAMETER
Output Current
Input Bias Current
Maximum Output Voltage
Output Disable Threshold
FB Low Foldback Threshold
-3dB Bandwidth
CURRENT SENSE
Threshold Voltage
V
CS(TH)
CS+ = VCC, FB Forced to V
OUT
- 3%
0.8
≤
COMP
≤
1V
Current Limit Foldback Voltage
∆V
COMP
/∆V
CS
Input Bias Current
Response Time
POWER GOOD COMPARATOR
Undervoltage Threshold
Overvoltage Threshold
Output Voltage Low
Response Time
PWM OUTPUTS
Output Voltage Low
Output Voltage High
Output Current
Duty Cycle Limit, by Design
.
Recommended Operating Conditions, Unless Otherwise Noted
SYMBOL
I
O(ERR)
I
FB
V
COMP(MAX)
FB Forced to V
OUT
- 3%
V
COMP(OFF)
V
FB(LOW)
BW
ERR
COMP = Open
TEST CONDITIONS
FB Forced to V
OUT
- 3%
MIN
-
-
-
560
375
-
TYP
1
5
3.0
720
425
500
MAX
-
100
-
800
500
-
UNITS
mA
nA
V
mV
mV
kHz
69
-
37
-
-
-
79
0
47
25
0.5
50
89
15
58
-
5.0
-
mV
mV
mV
V/V
µA
ns
V
CS(FOLD)
n
i
I
CS+
, I
CS-
t
CS
FB
≤
375mV
1 V
≤
V
COMP
≤ 3V
CS+ = CS- = VCC
CS+ - (CS-)
≥
89mV to PWM Going Low
V
PWRGD(UV)
Percent of Nominal Output
V
PWRGD(OV)
Percent of Nominal Output
V
OL(PWRGD)
I
PWRGD(SINK)
= 100µA
76
114
-
-
82
124
30
200
88
134
200
-
%
%
mV
ns
V
OL(PWM)
V
OH(PWM)
I
PWM
D
MAX
I
PWM(SINK)
= 400µA
I
PWM(SOURCE)
= 400µA
-
4.5
0.4
100
5.0
1
-
500
5.5
-
50
mV
V
mA
%
Per Phase, Relative to f
CT
-
VOLTAGE IDENTIFICATION CODE AT
PROCESSOR PINS
VID25mV
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
VID3
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
VID2
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
VID1
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
VID0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
V
CC
CORE
(VDC)
1.050
1.075
1.100
1.125
1.150
1.175
1.200
1.225
1.250
1.275
1.300
1.325
1.350
1.375
1.400
1.425
VOLTAGE IDENTIFICATION CODE AT
PROCESSOR PINS
VID25mV
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
VID3
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
VID2
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
VID1
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
VID0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
V
CC
CORE
(VDC)
1.450
1.475
1.500
1.525
1.550
1.575
1.600
1.625
1.650
1.675
1.700
1.725
1.750
1.775
1.800
1.825
4
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