ISL6562
Block Diagram
REF
VCC
3V REFERENCE
PWRGD
+
X 0.82
UVLO and
BIAS CIRCUITS
OSCILLATOR
CT
PWM1
CONTROL
LOGIC
PWM2
CMP
-
UV
+
X1.24
VID3
VID2
VID1
VID0
VID25mV
FB
COMP
D/A
+
E/A
-
OVP
+
CS+
CS-
-
-
GND
Simplified Power System Diagram
FB
PWM 1
SYNCHRONOUS
RECTIFIED BUCK
CHANNEL
MICROPROCESSOR
PWM 2
SYNCHRONOUS
RECTIFIED BUCK
CHANNEL
Current Sense Comparator. Pulling this pin to ground
disables the oscillator and drives both PWM outputs low.
FB (Pin 7)
Inverting input of the internal transconductance error
amplifier.
ISL6562
CT (Pin 8)
A capacitor on this terminal sets the frequency of the internal
oscillator.
VID
Functional Pin Description
VID3 1
VID2 2
VID1 3
VID0 4
VID25mV 5
COMP 6
FB 7
CT 8
16 VCC
15 REF
14 CS-
13 PWM1
12 PWM2
11 CS+
10 PWRGD
9 GND
GND (Pin 9)
Bias and reference ground. All signals are referenced to this
pin.
PWRGD (Pin 10)
Open drain connection. A high voltage level at this pin with a
resistor connected to this terminal and VCC indicates that
CORE voltage is at the proper level,
CS+ (Pin 11) and CS- (Pin 14)
These inputs monitor the
supply current to the converter positive input voltage. CS+ is
connected directly to the decoupled supply voltage and
current sampling resistor. CS- is connected to the other end
of the current sampling resistor and the upper drains of the
series transistors.
VID3 (Pin 1), VID2 (Pin 2), VID1 (Pin 3), VID0 (Pin 4)
and VID25mV (Pin 5)
Voltage Identification inputs from microprocessor. These pins
respond to TTL and 3.3V logic signals. The ISL6562 decodes
VID bits to establish the output voltage. See Table 1.
PWM2 (Pin 12) and PWM1 (Pin 13)
PWM outputs connected to the gate driver ICs.
REF (Pin 15)
Three volt supply used to bias the output of the
transconductance amplifier.
COMP (Pin 6)
Output of the internal transconductance error amplifier.
Voltage at this terminal sets the output current level of the
VCC (Pin 16)
Bias supply. Connect this pin to a 12V supply.
2
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