ISL705ARH, ISL705BRH, ISL705CRH, ISL706ARH, ISL706BRH, ISL706CRH
Pin Configurations
ISL705ARH, ISL706ARH
(8 LD FLATPACK)
TOP VIEW
ISL705BRH, ISL706BRH
(8 LD FLATPACK)
TOP VIEW
ISL705CRH, ISL706CRH
(8 LD FLATPACK)
TOP VIEW
MR
WDO
RST
WDI
PFO
MR
WDO
RST_OD
WDI
MR
1
2
3
4
8
7
6
5
WDO
RST
WDI
PFO
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
V
V
V
DD
DD
DD
GND
PFI
GND
PFI
GND
PFI
PFO
Pin Descriptions
ISL705ARH
ISL705BRH
ISL705CRH
ISL706CRH
ISL706ARH
ISL706BRH
NAME
MR
DESCRIPTION
1
2
1
2
1
Manual Reset. MR is an active-low, debounced, TTL/CMOS compatible input that may
be used to trigger a reset pulse.
2
V
Power Supply. V is a supply voltage input that provides power to all internal circuitry.
DD
This input is also monitored and used to trigger a reset pulse. Reset is guaranteed
DD
operable after V rises above 1.2V.
DD
3
4
3
4
3
4
GND
PFI
Ground. GND is a supply voltage return for all internal circuitry. This return establishes
the reference level for voltage detection and should be connected to signal ground.
Power Fail Input. PFI is an input to a threshold detector, which may be used to monitor
another supply voltage level. The threshold of the detector (V ) is 1.25V in the
PFI
ISL705ARH/BRH/CRH and 0.6V in the ISL706ARH/BRH/CRH.
5
6
5
6
5
6
PFO
WDI
Power Fail Output. PFO is an active-low, push-pull output of a threshold detector that
indicates the voltage at the PFI pin is less than V
.
PFI
Watchdog Input. WDI is a tri-state input that monitors microprocessor activity. If the
microprocessor does not toggle WDI within 1.6s and WDI is not tri-stated, WDO goes
low. As long as reset is asserted or WDI is tri-stated, the watchdog timer will stay cleared
and will not count. As soon as reset is released and WDI is driven high or low, the timer
will start counting. Floating WDI or connecting WDI to a high impedance tri-state buffer
disables the watchdog feature.
7
-
-
RST
Reset. RST is an active-low, push-pull output that is guaranteed to be low once V
DD
reaches 1.2V. As V rises, RST stays low. When V rises above a 4.65V
DD DD
(ISL705ARH/BRH/CRH) or 3.08V (ISL706ARH/BRH/CRH) reset threshold, an internal
timer releases RST after about 200ms. RST pulses low whenever V goes below the
DD
reset threshold. If a brownout condition occurs in the middle of a previously initiated
reset pulse, the pulse will continue for at least 140ms. On power-down, once V falls
DD
below the reset threshold, RST goes low and is guaranteed low until V drops below
DD
1.2V.
-
-
7
-
-
RST
Reset. RST is an active-high, push-pull output. RST is the inverse of RST.
7
RST_OD Reset. RST_OD is an active-low, open-drain output that goes low when reset is asserted.
This pin may be pulled up to V with a resistor consistent with the sink and leakage
DD
current specifications of the output. Behavior is otherwise identical to the RST pin.
8
8
8
WDO
Watchdog Output. WDO is an active-low, push-pull output that goes low if the
microprocessor does not toggle WDI within 1.6s and WDI is not tri-stated. WDO is
usually connected to the non-maskable interrupt input of a microprocessor. When V
DD
drops below the reset threshold, WDO will go low whether or not the watchdog timer
has timed out. Reset is simultaneously asserted, thus preventing an interrupt. Since
floating WDI disables the internal timer, WDO goes low only when V drops below the
DD
reset threshold, thus functioning as a low line output.
FN7662.0
September 15, 2011
2
INTERSIL [ Intersil ]
