ISL6443
position the load main pole somewhere within one decade
lower than the amplifier zero frequency. With this type of
compensation plenty of phase margin is easily achieved due
to zero-pole pair phase ‘boost’.
Figure 18 shows the linear regulator (2.5V) startup waveform
and the PWM (3.3V) startup waveform.
Conditional stability may occur only when the main load pole
is positioned too much to the left side on the frequency axis
due to excessive output filter capacitance. In this case, the
ESR zero placed within the 1.2kHz to 30kHz range gives
some additional phase ‘boost’. Some phase boost can also
V
1V/DIV
1V/DIV
OUT2
be achieved by connecting capacitor C in parallel with the
Z
upper resistor R1 of the divider that sets the output voltage
value. Please refer to the output inductor and capacitor
selection sections for further details.
V
OUT3
Linear Regulator
The linear regulator controller is a transconductance
amplifier with a nominal gain of 2A/V. The N-channel
MOSFET output device can sink a minimum of 50mA. The
reference voltage is 0.8V. With zero volts differential at it’s
input, the controller sinks 21mA of current. An external PNP
transistor or PFET pass element can be used. The dominant
pole for the loop can be placed at the base of the PNP (or
gate of the PFET), as a capacitor from emitter to base
(source to gate of a PFET). Better load transient response is
achieved however, if the dominant pole is placed at the
output, with a capacitor to ground at the output of the
regulator.
FIGURE 18. LINEAR REGULATOR STARTUP WAVEFORM
60
50
40
30
Under no-load conditions, leakage currents from the pass
transistors supply the output capacitors, even when the
transistor is off. Generally this is not a problem since the
feedback resistor drains the excess charge. However,
20
charge may build up on the output capacitor making V
LDO
10
0
rise above its set point. Care must be taken to insure that the
feedback resistor’s current exceeds the pass transistors
leakage current over the entire temperature range.
0.84
0.79
0.8
0.82
0.83
0.85
0.81
FEEDBACK VOLTAGE (V)
The linear regulator output can be supplied by the output of
one of the PWMs. When using a PFET, the output of the
linear will track the PWM supply after the PWM output rises
to a voltage greater than the threshold of the PFET pass
device. The voltage differential between the PWM and the
FIGURE 19. LINEAR CONTROLLER GAIN
Base-Drive Noise Reduction
The high-impedance base driver is susceptible to system
noise, especially when the linear regulator is lightly loaded.
Capacitively coupled switching noise or inductively coupled
EMI onto the base drive causes fluctuations in the base
current, which appear as noise on the linear regulator’s
output. Keep the base drive traces away from the step-down
converter, and as short as possible, to minimize noise
coupling. A resistor in series with the gate drivers reduces
the switching noise generated by PWM. Additionally, a
bypass capacitor may be placed across the base-to-emitter
resistor. This bypass capacitor, in addition to the transistor’s
input capacitor, could bring in second pole that will de-
stabilize the linear regulator. Therefore, the stability
requirements determine the maximum base-to-emitter
capacitance.
linear output will be the load current times the r
.
DS(ON)
FN9044.1
14
October 4, 2005
INTERSIL [ Intersil ]
