DG441, DG442
Test Circuits and Waveforms
(Continued)
C
V+
+15V
V
S
IMPEDANCE
ANALYZER
V
D
f = 1MHz
V-
-15V
C
IN
X
0V, 2.4V
GND
FIGURE 5. SOURCE/DRAIN CAPACITANCES TEST CIRCUIT
Application Information
GAIN ERROR IS DETERMINED ONLY BY THE RESISTOR TOLERANCE.
OP AMP OFFSET AND CMRR WILL LIMIT ACCURACY OF CIRCUIT.
+15V
-15V
FET INPUT
7
4
OP AMP 3
2
+15V
13
2
GAIN
1
A
V
= 1
GAIN
2
A
V
= 10
GAIN
3
A
V
= 20
GAIN
4
A
V
= 100
1
15
16
10
9
7
8
V-
4
-15V
GND
5
6
R
4
1kΩ
11
R
3
4kΩ
14
+15V
R
2
5kΩ
V
IN
+
1/4 DG442
S
X
D
X
+
C
H
3
R
1
90kΩ
V
IN
6
V
OUT
-
V
OUT
-
IN
X
1 = SAMPLE
0 = HOLD
-15V
V
OUT
R
1
+
R
2
+
R
3
+
R
4
--------------- = ------------------------------------------------ =
100 with SW
4
closed
-
-
V
IN
R
4
FIGURE 6. PRECISION WEIGHTED RESISTOR
PROGRAMMABLE GAIN AMPLIFIER
FIGURE 7. OPEN LOOP SAMPLE AND HOLD
7
FN3281.10
November 20, 2006
INTERSIL [ INTERSIL CORPORATION ]
