DG408, DG409
Test Circuits and Waveforms
+15V
+2.4V
V+
EN ALL S AND D
A
A
0
LOGIC
INPUT
50Ω
A
1
A
2
DG408
DG409
GND
V-
D, D
B
300Ω
+5V (V
S
)
V
S
SWITCH
OUTPUT
V
O
35pF
SWITCH
OUTPUT
V
O
0V
t
OPEN
80%
80%
LOGIC
INPUT
3V
0V
(Continued)
t
r
< 20ns
t
f
< 20ns
-
15V
FIGURE 3A. TEST CIRCUIT
FIGURE 3B. MEASUREMENT POINTS
FIGURE 3. BREAK-BEFORE-MAKE INTERVAL
+15V
LOGIC
INPUT
D
C
L
10nF
V
-
∆V
O
IS THE MEASURED VOLTAGE DUE
TO CHARGE TRANSFER ERROR, Q
Q = C
L
x
∆V
O
V
O
SWITCH
OUTPUT
∆V
O
3V
0V
R
GEN
S
X
V
GEN
CHANNEL
SELECT
A
0
A
1
A
2
EN GND
V+
ON
OFF
LOGIC INPUT
-
15V
FIGURE 4A. TEST CIRCUIT
FIGURE 4. CHARGE INJECTION
FIGURE 4B. MEASUREMENT POINTS
0V +15V
V
IN
S
X
|
|
S
8
A
2
SIGNAL
GENERATOR
A
1
A
0
GND
V
-
EN
V+
1kΩ
V
O
D
1kΩ
SIGNAL
GENERATOR
V
IN
5V +15V
S
1
S
X
|
|
S
8
A
2
A
1
A
0
EN
V+
V
O
D
1kΩ
V
-
-
15V
ANALYZER
V
OUT
OFF ISOLATION = 20 Log -----------------
V IN
ANALYZER
GND
-
15V
V OUT
CROSSTALK = 20 Log -----------------
V
IN
FIGURE 5. OFF ISOLATION
FIGURE 6. CROSSTALK
7
FN3283.8
June 13, 2006
INTERSIL [ INTERSIL CORPORATION ]
